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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8 Issue 2, April 2003

Tutorial: Compiling concurrent languages for sequential processors
Stephen A. Edwards
Pages: 141-187
DOI: 10.1145/762488.762489
Embedded systems often include a traditional processor capable of executing sequential code, but both control and data-dominated tasks are often more naturally expressed using one of the many domain-specific concurrent specification languages. This...

Rectilinear block placement using B*-trees
Guang-Ming Wu, Yun-Chih Chang, Yao-Wen Chang
Pages: 188-202
DOI: 10.1145/762488.762490
Due to the layout complexity in modern VLSI designs, integrated circuit blocks may not be rectangular. However, literature on general rectilinear block placement is still quite limited. In this article, we present approaches for handling the...

Minimum delay optimization for domino logic circuits---a coupling-aware approach
Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang
Pages: 203-213
DOI: 10.1145/762488.762491
Minimum delay associated with the hold time requirement is of concern to circuit designers, since race-through hazards are inherent in any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property...

Compacting sequences with invariant transition frequencies
Ali Pinar, C. L. Liu
Pages: 214-221
DOI: 10.1145/762488.762492
Simulation-based power estimation is commonly used for its high accuracy despite excessive computation times. Techniques have been proposed to speed it up by compacting an input sequence while preserving its power-consumption characteristics. We...

Sequential optimization in the absence of global reset
Vigyan Singhal, Carl Pixley, Adnan Aziz, Shaz Qadeer, Robert Brayton
Pages: 222-251
DOI: 10.1145/762488.762493
We study the problem of optimizing synchronous sequential circuits. There have been previous efforts to optimize such circuits. However, all previous attempts make implicit or explicit assumptions about the design or the environment of the design....

Compiler optimization on VLIW instruction scheduling for low power
Chingren Lee, Jenq Kuen Lee, Tingting Hwang, Shi-Chun Tsai
Pages: 252-268
DOI: 10.1145/762488.762494
In this article, we investigate compiler transformation techniques regarding the problem of scheduling VLIW instructions aimed at reducing power consumption of VLIW architectures in the instruction bus. The problem can be categorized into two types:...