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SOC test architecture design for efficient utilization of test bandwidth
Sandeep Kumar Goel, Erik Jan Marinissen
This article deals with the design of on-chip architectures for testing large system chips (SOCs) for manufacturing defects in a modular fashion. These architectures consist of wrappers and test access mechanisms (TAMs). For an SOC with specified...
Test vector decomposition-based static compaction algorithms for combinational circuits
Aiman H. El-Maleh, Yahya E. Osais
Testing system-on-chips involves applying huge amounts of test data, which is stored in the tester memory and then transferred to the chip under test during test application. Therefore, practical techniques, such as test compression and compaction,...
On test data volume reduction for multiple scan chain designs
Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz
We consider issues related to the reduction of scan test data in designs with multiple scan chains. We propose a metric that can be used to evaluate the effectiveness of procedures for reducing the scan data volume. The metric compares the achieved...
Test data compression using dictionaries with selective entries and fixed-length indices
Lei Li, Krishnendu Chakrabarty, Nur A. Touba
We present a dictionary-based test data compression approach for reducing test data volume in SOCs. The proposed method is based on the use of a small number of ATE channels to deliver compressed test patterns from the tester to the chip and to drive...
Multimode scan: Test per clock BIST for IP cores
Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan
Built-in self-test (BIST) is an attractive design-for-test methodology for core-based SoC design because of the minimal need for test access when tests are generated and evaluated within the core itself. However, the scan based logic BIST approach...
Testing high-performance pipelined circuits with slow-speed testers
Muhammad Nummer, Manoj Sachdev
This article presents a methodology for testing high-performance pipelined circuits with slow-speed testers. The technique uses a clock timing circuit to control data transfer in the pipeline in test mode. The technique adds no extra hardware in the...
BIST and production testing of ADCs using imprecise stimulus
Kumar Parthasarathy, Turker Kuyel, Dana Price, Le Jin, Degang Chen, Randall Geiger
A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear...
A circuit level fault model for resistive bridges
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
Delay faults are an increasingly important test challenge. Modeling bridge faults as delay faults helps delay tests to detect more bridge faults. Traditional bridge fault models are incomplete because these models only model the logic faults or these...
A data acquisition methodology for on-chip repair of embedded memories
Dirk Niggemeyer, Elizabeth M. Rudnick
Systems-on-Chips often contain a large amount of embedded memory. In order to obtain sufficiently high yield, efficient diagnosis and repair facilities are needed for the memories. A novel and efficient approach for collecting complete failure data...
A multiple bit upset tolerant SRAM memory
Gustavo Neuberger, Fernanda de Lima, Luigi Carro, Ricardo Reis
SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a...