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Formal hardware specification languages for protocol compliance verification
Annette Bunker, Ganesh Gopalakrishnan, Sally A. Mckee
The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling...
Power minimization algorithms for LUT-based FPGA technology mapping
Hao Li, Srinivas Katkoori, Wai-Kei Mak
We study the technology mapping problem for LUT-based FPGAs targeting at power minimization. The problem has been proved to be NP-hard previously. Therefore, we present an efficient heuristic algorithm to generate low-power mapping solutions. The key...
Fast memory bank assignment for fixed-point digital signal processors
Jeonghun Cho, Yunheung Paek, David Whalley
Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single...
Manhattan-diagonal routing in channels and switchboxes
Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya
New techniques are presented for routing straight channels, L-channels, switchboxes, and staircase channels in a two-layer Manhattan-diagonal (MD) model with tracks in horizontal, vertical, and ± 45° directions. First, an...
A BNF-based automatic test program generator for compatible microprocessor verification
Lieh-Ming Wu, Kuochen Wang, Chuang-Yi Chiu
A novel Backus-Naur-form- (BNF-) based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. We use X86 architecture to illustrate our design method. Our method is equally...