Massoud Pedram
			Department of Electrical Engineering University of Southern California EEB 344, 3740 McClintock Ave, Los Angeles CA 90089-2562 , USA Tel: +1 213 740-4458 Fax: +1 213 740-9803 Email: pedram@usc.edu http://atrak.usc.edu/~massoud

System-Level Synthesis, SoC design, and Networks on Chip

	Davide Bertozzi
			Engineering Department University of Ferrara Via Saragat, 1, 44122 Ferrara FE, Italy Tel: +39 0532 974832 Fax: +39 0532 974870 Email: davide.bertozzi@unife.it Areas of interest: Networks-on-chip, on-chip communication, MpSoC design

	Bill Lin
			Department of Electrical and Computer Engineering University of California, San Diego La Jolla, CA 92093-0407, USA Tel: +1 (858) 822-1383 Email: billlin@ece.ucsd.edu http://cwc.ucsd.edu/~billlin Areas of interest: Network and VLSI architecture: design of data networks, high-performance switches and routers, high-speed network measurement mechanisms, and on-chip interconnection networks.

	Shaahin Hessabi
			Department of Computer Engineering Sharif University of Technology Tehran, Iran Email: hessabi@sharif.edu http://sharif.edu/~hessabi Areas of interest: SoC design, and networks on chip, testing and design for testability, digital design, FPGA synthesis and reconfigurable systems, real-time systems, embedded software and systems , hardware/software codesign.

Real-Time Systems, Embedded Software and Systems , Hardware/Software Codesign

	Christoph Kirsch
			Department of Computer Sciences University of Salzburg Jakob-Haringer-Str. 2, 5020 Salzburg, Austria Tel: +1 (510) 859-3634 Fax: +43-662-8044-611 Email: ck@cs.uni-salzburg.at http://www.cs.uni-salzburg.at/~ck/ Areas of interest: Principled engineering of concurrent software systems, Embedded, real-time, and concurrent programming, Memory management and virtual execution environments.

	Jurgen Teich
			Department of Computer Science University of Erlangen-Nuremberg Am Weichselgarten 3, 91058 Erlangen, Germany Tel: +49 9131 85-25150 Fax: +49 9131 85-25149 Email: teich@cs.fau.de http://www12.informatik.uni-erlangen.de/people/teich/ Areas of interest: Embedded Systems, Scheduling Theory and Optimization, Massively Parallel VLSI Architectures, Invasive Computing

Reliable Computing and Secure Systems

	Patrick Schaumont
			Bradley Department of Electrical and Computer Engineering Virginia Tech 302 Whittemore Hall (0111), Blacksburg, VA 24061, USA. Tel: +1 (540) 231-3553 Fax: +1 (540) 231-3362 Email: schaum@vt.edu http://www.ece.vt.edu/schaum Areas of interest: Secure and Embedded Systems, Cryptographic Hardware and Software, Implementation Attacks and Countermeasures, Security-aware Design Methods.

Power Analysis and Optimization

	Massimo Poncino
			Dipartimento di Automatica e Informatica Politecnico di Torino Corso Duca degli Abruzzi 24, 10129 Torino, Italy. Tel: +39-011-0907011 Fax: +39-011-0907099 Email: massimo.poncino@polito.it http://staff.polito.it/massimo.poncino/ Areas of interest: Logic, RTL and Behavioral Synthesis; Multi-Processor System-on-Chip, Computer Architecture and Enterprise Computing; Energy Efficient Design Methodologies and Green Computing.

	Yung-Hsiang Lu
			Department of Electrical and Computer Engineering Purdue University 465 Northwestern Avenue, EE Building, West Lafayette, IN 47907-2035, USA Tel: 765-494-2668 Email: yunglu@purdue.edu http://engineering.purdue.edu/HELPS/ Areas of interest: Low power systems, mobile computing, multimedia, parallel processing

	Qinru Qiu
			Department of Electrical Engineering and Computer Science Syracuse University Center for Science and Technology 4-206, Syracuse, NY 13244 Tel: 315-443-1836 Email: qiqiu@syr.edu http://hydrogen.syr.edu/~qqiu/ Areas of interest: Power and thermal management, energy harvesting systems, neuromorphic computing, real-time embedded systems.

Energy Efficient Design Methodologies and Low Power Systems

	Massimo Alioto
			Information Engineering Department University of Siena Via Roma, 56 53100, Siena - Italy Tel: +39-0577-234850 (ext. 1004) Fax: +39-0577-233602 Email: malioto@dii.unisi.it http://www.dii.unisi.it/~malioto/ Areas of interest: VLSI circuit modeling for design automation, Ultra-low power VLSI design, Variability-aware circuit techniques and models, VLSI design in emerging technologies.

	Lin Zhong
			Rice University 6100 Main St, MS-380 Houston, TX 77005 Email: lzhong@rice.edu http://www.ruf.rice.edu/~lzhong/ Areas of interest: Energy efficient design methodologies and low power systems, power analysis and optimization, multi-processor system-on-chip, computer architectural and micro-architectural design.

Multi-Processor System-on-Chip, Computer Architectural and Micro-architectural Design

	Murali Annavaram
			Ming-Hsieh Department of Electrical Engineering University of Southern California Los Angeles CA 90089-2562, USA Tel: +1 (213) 740-3299 Email: annavara@usc.edu http://www.usc.edu/dept/ee/scip/ Areas of interest: Energy efficient sensor management for body area sensor networks, computer systems architecture exploring reliability challenges in the future CMOS technologies.

Simulation, Validation, and Formal Verification

	Wolfgang Kunz
			Dept. of Electrical & Computer Engineering University of Kaiserslautern P.O. Box 3049, 67653 Kaiserslautern, Germany Tel: +49 (631) 205-2603 Fax: +49 (631) 205-4782 Email: kunz@eit.uni-kl.de http://www.eit.uni-kl.de/eis/personen/kunz/ Areas of interest: Formal verification, logic synthesis

	Prabhat Mishra
			Dept. of Computer and Information Science and Engineering University of Florida P.O. Box 116120, Gainesville, FL 32611-6120, USA Tel: +1 (352) 505-1880 Fax: +1 (352) 392-1220 Email: prabhat@cise.ufl.edu http://www.cise.ufl.edu/~prabhat Areas of interest: Hardware verification, post-silicon validation, embedded systems.

	Pete Manolios
			College of Computer and Information Science Northeastern University 360 Huntington Avenue, Boston, Massachusetts 02115 USA Tel: +1 617 373 3694 Fax: +1 617 373 5121 Email: pete@ccs.neu.edu http://www.ccs.neu.edu/home/pete/ Areas of interest: formal methods, hardware verification, software verification, decision procedures, theorem proving

Logic, RTL and Behavioral Synthesis

	Paolo Ienne
			School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne (EPFL) Station 14, CH-1015 Lausanne, Switzerland Tel: +41 21 69 32625 / 32641 Fax: +41 21 69 95263 Email: paolo.ienne@epfl.ch http://people.epfl.ch/paolo.ienne Areas of interest: Customizable Processors, Configurable Computing, Design Methodologies for Computer Arithmetic, Multiprocessors on Chip.

	Sunil Khatri
			Department of Electrical and Computer Engineering Texas A&M University College Station, Texas 77843 Tel: +1 (979) 845-8371 Fax: +1 (979) 845-2630 Email: sunilkhatri@tamu.edu http://www.ece.tamu.edu/~sunil/ Areas of interest: Logic, RTL and Behavioral Synthesis, Low Power, Testing, Circuit Design, Clocking, Radiation Effects in VLSI.

	Youngsoo Shin
			Department of Electrical Engineering Korea Advanced Institute of Science and Technology (KAIST) 291 Daehak-ro, Yuseong-gu, Daejeon 305-701, Korea Tel: +82-42-350-3479 Fax: +82-42-351-9895 Email: youngsoo@ee.kaist.ac.kr http://dtlab.kaist.ac.kr/wiki/index.php/Member-Professor Areas of interest: Low-power design and design tools, high-level synthesis, sequential synthesis, and structured ASIC.

Physical Design and Physical Synthesis

	Chris Chu
			Department of Electrical and Computer Engineering Iowa State University 2215 Coover Hall, Ames, IA 50011-3060, USA Tel: +1 (515) 294-3490 Fax: +1 (515) 294-1152 Email: cnchu@iastate.edu http://home.eng.iastate.edu/~cnchu Areas of interest: Computer-aided design of VLSI circuits; Design and analysis of algorithms; Discrete and continuous optimization.

	Jiang Hu
			Department of Electrical and Computer Engineering Texas A&M University College Station, TX 77843-3128, USA Tel: +1 979-847-8768 Fax: +1 979-845-2630 Email: jianghu@ece.tamu.edu http://dropzone.tamu.edu/~jhu/ Areas of interest: Physical design, design for manufacturability, clock network synthesis, interconnect and circuit optimization.

	Ting-Chi Wang
			Department of Computer Science National Tsing Hua University, Taiwan Hsinchu, Taiwan Tel: + 886-3-5742963 Fax: + 886-3-5723694 Email: tcwang@cs.nthu.edu.tw http://www.cs.nthu.edu.tw/~tcwang Areas of interest: Floorplanning, placement, routing, physical design for manufacturability and yield.

	Evangeline Fung-Yu Young
			Department of Computer Science and Engineering The Chinese University of Hong Kong Shatin New Territories, Hong Kong Email: fyyoung@cse.cuhk.edu.hk http://www.cse.cuhk.edu.hk/~fyyoung/ Areas of interest: Floorplanning, placement, routing, biochip synthesis, analog layout, clock routing, algorithms and optimization

Combinatorial Optimizations

	Patrick Madden
			Department of Computer Science State University of New York at Binghamton P.O. Box 6000, Binghamton, NY 13902, USA. Tel: +1 (607) 777-2943 Fax: +1 (607) 777-4729 Email: pmadden@acm.org http://www.cs.binghamton.edu/~pmadden Areas of interest: Optimization for NP-hard problems.

	Jens Vygen
			Research Institute for Discrete Mathematics University of Bonn Lennéstr. 2, 53113 Bonn, Germany Email: vygen@or.uni-bonn.de http://www.or.uni-bonn.de/~vygen/ Areas of interest: Physical design, combinatorial optimization, placement, routing, timing optimization.

Testing and Design for Testability

	Sandip Kundu
			Dept. of Electrical & Computer Engineering University of Massachusetts 151 Holdsworth Way, Amherst MA 01003-9284, USA Tel: +1 (413) 577-3309 Fax: +1 (540) 231-3362 Email: kundu@ecs.umass.edu http://www.ecs.umass.edu/~kundu/ Areas of interest: Computer Architecture, VLSI CAD and Design Methodologies, Circuit Design & Test, Energy Systems and Smart Grid.

	Mohammad Tehranipoor
			Departments of Electrical and Computer Engineering University of Connecticut 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA Email: tehrani@engr.uconn.edu http://www.engr.uconn.edu/~tehrani/ Areas of interest: VLSI Testing, low-power test, delay test, design for testability and built-in self-test (bist), hardware security and trust, reliability analysis.

	Cecilia Metra
			Department of Electrical, Electronic, and Information Engineering University of Bologna Viale Risorgimento 2, Bologna (Italy) Tel: + 39 051 209 3013 Fax: + 39 051 209 3073 Email: cmetra@deis.unibo.it http://www-micro.deis.unibo.it/cgi-bin/user?metra Areas of interest: On-line testing, fault tolerance, fault modeling, error resilient systems, photovoltaic systems.

Digital Design, VLSI architectures, including Mixed-Signal Circuits and Systems

	Chi-Ying Tsui
			Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Clear Water Bay, New Territories, Hong Kong SAR, China. Tel: + 39 051 209 3013 Fax: + 39 051 209 3073 Email: eetsui@ee.ust.hk http://www.cpeg.ust.hk/~eetsui/ Areas of interest: Low power system design, energy efficient design methodology, network on chip and soc design methodology, power analysis and synthesis, computer architectural and micro-architectural design, embedded system design.

FPGA Synthesis, Reconfigurable Systems, and Custom Computing

	Deming Chen
			Department of Electrical and Computer Engineering University of Illinois, Urbana-Champaign 410 Coordinated Science Laboratory, 1308 W Main St Urbana, Illinois 61801 Email: dchen@illinois.edu http://icims.csl.illinois.edu/~dchen/ Areas of interest: FPGA (architecture, application, cad), high-level synthesis and logic synthesis, gpu (application, compilation, modeling), nanotechnology and emerging technology (nanotube, graphene, nem, nvram, etc.)

TODAES Information Director

	Sudeep Pasricha
			Dept. of Electrical and Computer Engineering Colorado State University C103A Engineering Building, Fort Collins, CO 80523-1373, USA Tel: +1 970-491-0254 Fax: +1 970-491-2249 Email: sudeep@colostate.edu http://www.engr.colostate.edu/~sudeep/

TODAES Editorial Assistant