| Authors |
Article |
Downloads |
Volume (Issue), Year |
| Miodrag Potkonjak, Wayne Wolf |
A methodology and algorithms for the design of hard real-time multitasking ASICs |
275 |
4(4), October 1999 |
| Inki Hong, Miodrag Potkonjak, Ramesh Karri |
Power optimization using divide-and-conquer techniques for minimization of the number of operations |
145 |
4(4), October 1999 |
| Farinaz Koushanfar, Inki Hong, Miodrag Potkonjak |
Behavioral synthesis techniques for intellectual property protection |
125 |
10(3), July 2005 |
| Georgios Kornaros, Dionisios Pnevmatikatos |
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip |
113 |
18(2), March 2013 |
| Mingxuan Yuan, Zonghua Gu, Xiuqiang He, Xue Liu, Lei Jiang |
Hardware/software partitioning and pipelined scheduling on runtime reconfigurable FPGAs |
110 |
15(2), February 2010 |
| Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak |
Optimizing computations for effective block-processing |
86 |
5(3), July 2000 |
| Liang Shi, Jianhua Li, Chun Jason Xue, Xuehai Zhou |
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems |
54 |
18(1), January 2013 |
| Chia-Heng Tu, Shih-Hao Hung, Tung-Chieh Tsai |
MCEmu: A Framework for Software Development and Performance Analysis of Multicore Systems |
38 |
17(4), October 2012 |
| Amit Agarwal, Jason Cong, Brian Tagiku |
The survivability of design-specific spare placement in FPGA architectures with high defect rates |
34 |
18(2), March 2013 |
| Rico Backasch, Christian Hochberger, Alexander Weiss, Martin Leucker, Richard Lasslop |
Runtime verification for multicore SoC with high-quality trace data |
31 |
18(2), March 2013 |
| Authors |
Article |
Downloads |
Volume (Issue), Year |
| Yi Wang, Hui Liu, Duo Liu, Zhiwei Qin, Zili Shao, and Edwin H.-M. Sha |
Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip |
324 |
16(2), April 2011 |
| Jason Cong, Wei Jiang, Bin Liu, and Yi Zou |
Automatic memory partitioning and scheduling for throughput and power optimization |
306 |
16(2), April 2011 |
| Yuhao Zhu, Bo Wang, and Yangdong Deng |
Massively Parallel Logic Simulation with GPUs |
264 |
16(3), June 2011 |
| Muhammad Adeel Pasha, Steven Derrien, and Olivier Sentieys |
System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow |
238 |
17(1), January 2012 |
| Yiding Han, Koushik Chakraborty, Sanghamitra Roy, and Vilasita Kuntamukkala |
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm |
236 |
16(3), June 2011 |
| Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, and Yunheung Paek |
Memory access optimization in compilation for coarse-grained reconfigurable architectures |
236 |
16(4), October 2011 |
| Debapriya Chatterjee, Andrew Deorio, and Valeria Bertacco |
Gate-Level Simulation with GPU Computing |
221 |
16(3), June 2011 |
| Alper Sen |
Concurrency-oriented verification and coverage of system-level designs |
219 |
16(4), October 2011 |
| Tak-Yung Kim and Taewhan Kim |
Clock Tree synthesis for TSV-based 3D IC designs |
217 |
16(4), October 2011 |
| Rajdeep Bondade and Dongsheng Ma |
Hardware-Software Codesign of an Embedded Multiple-Supply Power Management Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation and Processing Scheme |
195 |
16(3), June 2011 |