| Article |
Volume (Issue) |
Downloads |
| Radio frequency identification prototyping |
13(2) |
323 |
| Processor virtualization for secure mobile terminals |
13(3) |
304 |
| Designing secure systems on reconfigurable hardware |
13(3) |
260 |
| Analysis and optimization of prediction-based flow control in networks-on-chip |
13(1) |
239 |
| A fuel-cell-battery hybrid for portable embedded systems |
13(1) |
235 |
| Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA |
13(3) |
216 |
| A retargetable parallel-programming framework for MPSoC |
13(3) |
198 |
| Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs |
13(4) |
191 |
| An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory |
13(3) |
167 |
| Efficiently scheduling runtime reconfigurations |
13(4) |
161 |
| Article |
Volume (Issue) |
Downloads |
| On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches |
12(3) |
209 |
| Binary synthesis |
12(3) |
184 |
| Probabilistic system-on-a-chip architectures |
12(3) |
169 |
| A framework for heterogeneous specification and design of electronic embedded systems in SystemC |
12(3) |
152 |
| PeaCE: A hardware-software codesign environment for multimedia embedded systems |
12(3) |
149 |
| Efficient power modeling and software thermal sensing for runtime temperature monitoring |
12(3) |
140 |
| A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs |
12(1) |
110 |
| MPSoC memory optimization using program transformation |
12(4) |
105 |
| Disjunctive image computation for software verification |
12(2) |
96 |
| ILP and heuristic techniques for system-level design on network processor architectures |
12(4) |
94 |
| Article |
Vol (I), Year |
Downloads |
Citations |
| Data and memory optimization techniques for embedded systems |
6(2), April 2001 |
568 |
80 |
| System-level power optimization: techniques and tools |
5(2), April 2000 |
547 |
78 |
| Power minimization in IC design: principles and applications |
1(1), Jan 1996 |
401 |
88 |
| Formal verification in hardware design: a survey |
4(2), April 1999 |
341 |
18 |
| A design automation and power estimation flow for RFID systems |
14(1), Jan'2009 |
339 |
0 |
| Radio frequency identification prototyping |
13(2) April 2008 |
323 |
1 |
| Processor virtualization for secure mobile terminals |
13(3), July 2008 |
304 |
1 |
| Behavioral synthesis techniques for intellectual property protection |
10(3), July 2005 |
265 |
2 |
| Designing secure systems on reconfigurable hardware |
13(3), July 2008 |
260 |
0 |
| On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems |
5(3), July 2000 |
255 |
25 |