Design Automation of Electronic Systems (TODAES)


Search Issue
enter search term and/or author name


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 9 Issue 4, October 2004

Experimental analysis of the fastest optimum cycle ratio and mean algorithms
Ali Dasdan
Pages: 385-418
DOI: 10.1145/1027084.1027085

Optimum cycle ratio (OCR) algorithms are fundamental to the performance analysis of (digital or manufacturing) systems with cycles. Some applications in the computer-aided design field include cycle time and slack optimization for circuits,...

Cache optimization for embedded processor cores: An analytical approach
Arijit Ghosh, Tony Givargis
Pages: 419-440
DOI: 10.1145/1027084.1027086

Embedded microprocessor cores are increasingly being used in embedded and mobile devices. The software running on these embedded microprocessor cores is often a priori known; thus, there is an opportunity for customizing the cache subsystem for...

Coordinated parallelizing compiler optimizations and high-level synthesis
Sumit Gupta, Rajesh Kumar Gupta, Nikil D. Dutt, Alexandru Nicolau
Pages: 441-470
DOI: 10.1145/1027084.1027087

We present a high-level synthesis methodology that applies a coordinated set of coarse-grain and fine-grain parallelizing transformations. The transformations are applied both during a pre-synthesis phase and during scheduling, with the objective...

Reusing an on-chip network for the test of core-based systems
Érika Cota, Luigi Carro, Marcelo Lubaszewski
Pages: 471-499
DOI: 10.1145/1027084.1027088

Networks-on-chip are likely to become the main communication platform of systems-on-chip. To cope with the growing complexity of the test of such systems, the authors propose the reuse of the on-chip network as a test access mechanism to the cores...

Achieving high encoding efficiency with partial dynamic LFSR reseeding
C. V. Krishna, Abhijit Jas, Nur A. Touba
Pages: 500-516
DOI: 10.1145/1027084.1027089

Previous forms of LFSR reseeding have been static (i.e., test application is stopped while each seed is loaded) and have required full reseeding (i.e., the length of the seed is equal to the length of the LFSR). A new form of LFSR reseeding is...

Segmented channel routability via satisfiability
William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew Kennings, Alan Coppola
Pages: 517-528
DOI: 10.1145/1027084.1027090

Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean...