Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 10 Issue 1, January 2005

Nikil Dutt
Pages: 1-2
DOI: 10.1145/1044111.1044112

Technology mapping and architecture evalution for k/m-macrocell-based FPGAs
Jason Cong, Hui Huang, Xin Yuan
Pages: 3-23
DOI: 10.1145/1044111.1044113
In this article, we study the technology mapping problem for a novel field-programmable gate array (FPGA) architecture that is based on k-input single-output programmable logic array- (PLA-) like cells, or, k/m-macrocells. Each cell in...

Bipartitioning and encoding in low-power pipelined circuits
Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai
Pages: 24-32
DOI: 10.1145/1044111.1044114
In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of...

A scheduling algorithm for optimization and early planning in high-level synthesis
Seda Ogrenci Memik, Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh
Pages: 33-57
DOI: 10.1145/1044111.1044115
Complexities of applications implemented on embedded and programmable systems grow with the advances in capacities and capabilities of these systems. Mapping applications onto them manually is becoming a very tedious task. This draws attention to...

Combinatorial techniques for mixed-size placement
S. N. Adya, Igor L. Markov
Pages: 58-90
DOI: 10.1145/1044111.1044116
While recent literature on circuit layout addresses large-scale standard-cell placement, the authors typically assume that all macros are fixed. Floorplanning techniques are very good at handling macros, but do not scale to hundreds of thousands of...

RL-huffman encoding for test compression and power reduction in scan applications
Mehrdad Nourani, Mohammad H. Tehranipour
Pages: 91-115
DOI: 10.1145/1044111.1044117
This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan test applications. This is achieved by using run-length encoding followed by Huffman encoding. This combination is...

A 4-geometry maze router and its application on multiterminal nets
Gene Eu Jan, Ki-Yin Chang, Su Gao, Ian Parberry
Pages: 116-135
DOI: 10.1145/1044111.1044118
The maze routing problem is to find an optimal path between a given pair of cells on a grid plane. Lee's algorithm and its variants, probably the most widely used maze routing method, fails to work in the 4-geometry of the grid plane. Our algorithm...

Algorithmic aspects of hardware/software partitioning
Péter Arató, Zoltán Ádám Mann, András Orbán
Pages: 136-156
DOI: 10.1145/1044111.1044119
One of the most crucial steps in the design of embedded systems is hardware/software partitioning, that is, deciding which components of the system should be implemented in hardware and which ones in software. Most formulations of the...

A unified method for phase shifter computation
Dimitri Kagaris
Pages: 157-167
DOI: 10.1145/1044111.1044120
Phase shifters are used to shift the bit sequences produced by the successive stages of a built-in test pattern generator (TPG) based on a linear finite state machine (LFSM) by a specified amount (phase shift) relative to the characteristic...

An efficient algorithm for finding the minimal-area FPGA technology mapping
Chi-Chou Kao, Yen-Tai Lai
Pages: 168-186
DOI: 10.1145/1044111.1044121
Minimum area is one of the important objectives in technology mapping for lookup table-based field-progrmmable gate arrays (FPGAs). Although there is an algorithm that can find an optimal solution in polynomial time for the minimal-area FPGA...