Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13 Issue 1, January 2008

Nikil Dutt
Article No.: 1
DOI: 10.1145/1297666.1297667

Introduction to special section on high-level design, validation, and test
Michael S. Hsiao, Robert B. Jones
Article No.: 2
DOI: 10.1145/1297666.1297668

Boosting interpolation with dynamic localized abstraction and redundancy removal
Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer
Article No.: 3
DOI: 10.1145/1297666.1297669

SAT--based Unbounded Model Checking based on Craig Interpolants is often able to overcome BDDs and other SAT--based techniques on large verification instances. Based on refutation proofs generated by SAT solvers, interpolants provide compact...

Automata-based assertion-checker synthesis of PSL properties
Marc Boulé, Zeljko Zilic
Article No.: 4
DOI: 10.1145/1297666.1297670

Assertion-based verification with languages such as PSL is gaining in importance. From assertions, one can generate hardware assertion checkers for use in emulation, simulation acceleration and silicon debug. We present techniques for checker...

C-testable bit parallel multipliers over GF(2m)
H. Rahaman, J. Mathew, D. K. Pradhan, A. M. Jabir
Article No.: 5
DOI: 10.1145/1297666.1297671

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple...

A tool for automatic detection of deadlock in wormhole networks on chip
Sami Taktak, Jean-Lou Desbarbieux, Emmanuelle Encrenaz
Article No.: 6
DOI: 10.1145/1297666.1297672

We present an extension of Duato's necessary and sufficient condition a routing function must satisfy in order to be deadlock-free, to support environment constraints inducing extra-dependencies between messages. We also present an original...

A new efficient retiming algorithm derived by formal manipulation
Hai Zhou
Article No.: 7
DOI: 10.1145/1297666.1297673

A new efficient algorithm is derived for the minimal period retiming by formal manipulation. Contrary to all previous algorithms, which used fixed period feasibility checking to binary-search a candidate range, the derived algorithm checks the...

Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes
Article No.: 8
DOI: 10.1145/1297666.1297674

We propose the probabilistic transfer matrix (PTM) framework to capture nondeterministic behavior in logic circuits. PTMs provide a concise description of both normal and faulty behavior, and are well-suited to reliability and error susceptibility...

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang
Article No.: 9
DOI: 10.1145/1297666.1297675

Scan chains are popularly used as the channels for silicon testing and debugging. However, they have also been identified as one of the culprits of silicon failure more recently. To cope with this problem, several scan chain diagnosis approaches...

Interrupt modeling for efficient high-level scheduler design space exploration
F. Ryan Johnson, Joann M. Paul
Article No.: 10
DOI: 10.1145/1297666.1297676

Single Chip Heterogeneous Multiprocessors executing a wide variety of software are increasingly common in consumer electronics. Because of the mix of real-time and best effort software across the entire chip, a key design element of these systems...

Analysis and optimization of prediction-based flow control in networks-on-chip
Umit Y. Ogras, Radu Marculescu
Article No.: 11
DOI: 10.1145/1297666.1297677

Networks-on-Chip (NoC) communication architectures have emerged recently as a scalable solution to on-chip communication problems. While the NoC architectures may offer higher bandwidth compared to traditional bus-based communication, their...

Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
Article No.: 12
DOI: 10.1145/1297666.1297678

As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses...

Wavelet-based dynamic power management for nonstationary service requests
A. Abbasian, S. Hatami, A. Afzali-Kusha, M. Pedram
Article No.: 13
DOI: 10.1145/1297666.1297679

In this article, a wavelet-based dynamic power management policy (WBDPM) is proposed. In this approach, the workload source (service requester) is modeled by a nonstationary time series which, in turn, represented by a nondecimated Haar wavelet as...

Synthesis of a novel timing-error detection architecture
Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, Tingting Hwang
Article No.: 14
DOI: 10.1145/1297666.1297680

Delay variation can cause a design to fail its timing specification. Ernst et al. [2003] observe that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be...

ReChannel: Describing and simulating reconfigurable hardware in systemC
Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf
Article No.: 15
DOI: 10.1145/1297666.1297681

With the ongoing integration of (dynamic) reconfiguration into current system models, new methodologies and tools are needed to help the designer during the development process. This article introduces a language extension for SystemC along with a...

Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov
Article No.: 16
DOI: 10.1145/1297666.1297682

Maintaining local caches coherently in shared-memory multiprocessors results in significant power consumption. The customization methodology we propose exploits the fact that in embedded systems, important knowledge is available to the system...

SoCDAL: System-on-chip design AcceLerator
Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Junhee Yoo, Kiyoung Choi, Xingguang Feng
Article No.: 17
DOI: 10.1145/1297666.1297683

Time-to-market pressure and the ever-growing design complexity of multiprocessor system-on-chips have demanded an efficient design environment that enables fast exploration of large design space. In this article, we introduce a new design...

Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective
Nicholas H. Zamora, Xiaoping Hu, Umit Y. Ogras, Radu Marculescu
Article No.: 18
DOI: 10.1145/1297666.1297684

Successful proliferation of multimedia-enabled devices and advances in very large-scale integration (VLSI) technology has spawned new research efforts in migrating video processing applications onto ever smaller and more inexpensive devices. This...

A fuel-cell-battery hybrid for portable embedded systems
Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma Vrudhula
Article No.: 19
DOI: 10.1145/1297666.1297685

This article presents our work on the development of a fuel cell (FC) and battery hybrid (FC-Bh) system for use in portable microelectronic systems. We describe the design and control of the hybrid system, as well as a dynamic power management...

Low-power gated and buffered clock network construction
Wei-Chung Chao, Wai-Kei Mak
Article No.: 20
DOI: 10.1145/1297666.1297686

We propose an efficient algorithm to construct a low-power zero-skew gated clock network, given the module locations and activity information. Unlike previous works, we consider masking logic insertion and buffer insertion simultaneously, and...

Optimizing wirelength and routability by searching alternative packings in floorplanning
Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou
Article No.: 21
DOI: 10.1145/1297666.1297687

Recent advances in VLSI technology have made optimization of the interconnect delay and routability of a circuit more important. We should consider interconnect planning as early as possible. We propose a postfloorplanning step to reduce the...

Chip placement in a reticle for multiple-project wafer fabrication
Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai
Article No.: 22
DOI: 10.1145/1297666.1297688

Chip placement in a reticle is crucial to the cost of a multiproject wafer run. In this article we develop several chip placement methods based on the volume-driven compatibility optimization (VOCO) concept, which maximizes dicing compatibility...