Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13 Issue 2, April 2008

Nikil Dutt
Article No.: 23
DOI: 10.1145/1344418.1344419

SAT-based ATPG using multilevel compatible don't-cares
Nikhil Saluja, Kanupriya Gulati, Sunil P Khatri
Article No.: 24
DOI: 10.1145/1344418.1344420

In a typical IC design flow, circuits are optimized using multilevel don't cares. The computed don't cares are discarded before Technology Mapping or Automatic Test Pattern Generation (ATPG). In this paper, we present two combinational ATPG...

A noniterative equivalent waveform model for timing analysis in presence of crosstalk
Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang
Article No.: 25
DOI: 10.1145/1344418.1344421

Due to the nonuniform interconnect scaling in the Deep Sub Micron (DSM) region, the coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. This couple capacitance introduces server crosstalk...

Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction
Jin-Tai Yan
Article No.: 26
DOI: 10.1145/1344418.1344422

It is well known that the problem of constructing a timing-driven rectilinear Steiner tree for any signal net is important in performance-driven designs and has been extensively studied. Until now, many efficient approaches have been proposed for...

An open-source binary utility generator
Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel Casarotto, Luiz C. V. Santos, Max Schultz, Olinto Furtado
Article No.: 27
DOI: 10.1145/1344418.1344423

Electronic system level (ESL) modeling allows early hardware-dependent software (HDS) development. Due to broad CPU diversity and shrinking time-to-market, HDS development can neither rely on hand-retargeting binary tools, nor can it rely on...

Reconfigurable content-based router using hardware-accelerated language parser
James Moscola, John W. Lockwood, Young H. Cho
Article No.: 28
DOI: 10.1145/1344418.1344424

This article presents a dense logic design for matching multiple regular expressions with a field programmable gate array (FPGA) at 10+ Gbps. It leverages on the design techniques that enforce the shortest critical path on most FPGA...

Radio frequency identification prototyping
Alex K. Jones, Swapna Dontharaju, Shenchih Tung, Leo Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle
Article No.: 29
DOI: 10.1145/1344418.1344425

While RFID is starting to become a ubiquitious technology, the variation between different RFID systems still remains high. This paper presents several prototyping environments for different components of radio frequency identification (RFID) tags...

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
Yu Hu, Yan Lin, Lei He, Tim Tuan
Article No.: 30
DOI: 10.1145/1344418.1344426

Field programmable dual-Vdd interconnects are effective in reducing FPGA power. We formulate the dual-Vdd-aware slack budgeting problem as a linear program (LP) and a min-cost network flow problem, respectively. Both algorithms reduce interconnect...

A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration
Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
Article No.: 31
DOI: 10.1145/1344418.1344427

In this article we focus on multiprocessor system-on-chip (MPSoC) architectures for human heart electrocardiogram (ECG) real time analysis as a hardware/software (HW/SW) platform offering an advance relative to state-of-the-art solutions. This is...

Heterogeneously tagged caches for low-power embedded systems with virtual memory support
Xiangrong Zhou, Peter Petrov
Article No.: 32
DOI: 10.1145/1344418.1344428

An energy-efficient data cache organization for embedded processors with virtual memory is proposed. Application knowledge regarding memory references is used to eliminate most tag translations. A novel tagging scheme is introduced, where both...

Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
Fang Liu, Sule Ozev, Plamen K. Nikolov
Article No.: 33
DOI: 10.1145/1344418.1344429

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances...

A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction
Lei Cheng, Deming Chen, Martin D. F. Wong
Article No.: 34
DOI: 10.1145/1344418.1344430

The Input vector control (IVC) technique is based on the observation that the leakage current in a CMOS logic gate depends on gate input state, and a good input vector is able to minimize leakage when the circuit is in sleep mode. The gate...

The optimization of kEP-SOPs: Computational complexity, approximability and experiments
Anna Bernasconi, Valentina Ciriani, Roberto Cordone
Article No.: 35
DOI: 10.1145/1344418.1344431

We propose a new algebraic four-level expression called k-EXOR-projected sum of products (kEP-SOP). The optimization of a kEP-SOP is NPNP-hard, but can be approximated within a fixed performance guarantee in polynomial...

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies
R. Iris Bahar, Krishnendu Chakrabarty
Article No.: 36
DOI: 10.1145/1344418.1344432