Design Automation of Electronic Systems (TODAES)


Search Issue
enter search term and/or author name


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 13 Issue 3, July 2008

Nikil Dutt
Article No.: 37
DOI: 10.1145/1367045.1367046

Introduction to the special section on demonstrable software systems and hardware platforms II
Alex K. Jones, Robert Walker
Article No.: 38
DOI: 10.1145/1367045.1367047

A retargetable parallel-programming framework for MPSoC
Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek
Article No.: 39
DOI: 10.1145/1367045.1367048

As more processing elements are integrated in a single chip, embedded software design becomes more challenging: It becomes a parallel programming for nontrivial heterogeneous multiprocessors with diverse communication architectures, and design...

Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal
Article No.: 40
DOI: 10.1145/1367045.1367049

Future applications for embedded systems demand chip multiprocessor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are...

Implementing the scale vector-thread processor
Ronny Krashinsky, Christopher Batten, Krste Asanović
Article No.: 41
DOI: 10.1145/1367045.1367050

The Scale vector-thread processor is a complexity-effective solution for embedded computing which flexibly supports both vector and highly multithreaded processing. The 7.1-million transistor chip has 16 decoupled execution clusters, vector load...

Specification-driven directed test generation for validation of pipelined processors
Prabhat Mishra, Nikil Dutt
Article No.: 42
DOI: 10.1145/1367045.1367051

Functional validation is a major bottleneck in pipelined processor design due to the combined effects of increasing design complexity and lack of efficient techniques for directed test generation. Directed test vectors can reduce overall...

An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory
Yongsoo Joo, Youngjin Cho, Donghwa Shin, Jaehyun Park, Naehyuck Chang
Article No.: 43
DOI: 10.1145/1367045.1367052

Memory devices often consume more energy than microprocessors in current portable embedded systems, but their energy consumption changes significantly with the type of transaction, data values, and access timing, as well as depending on the total...

Designing secure systems on reconfigurable hardware
Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Tim Sherwood
Article No.: 44
DOI: 10.1145/1367045.1367053

The extremely high cost of custom ASIC fabrication makes FPGAs an attractive alternative for deployment of custom hardware. Embedded systems based on reconfigurable hardware integrate many functions onto a single device. Since embedded designers...

Automatic verification of safety and liveness for pipelined machines using WEB refinement
Panagiotis Manolios, Sudarshan K. Srinivasan
Article No.: 45
DOI: 10.1145/1367045.1367054

We show how to automatically verify that complex pipelined machine models satisfy the same safety and liveness properties as their instruction-set architecture (ISA) models by using well-founded equivalence bisimulation (WEB) refinement. We show...

Postplacement voltage assignment under performance constraints
Huaizhi Wu, Martin D.F. Wong, Wilsin Gosti
Article No.: 46
DOI: 10.1145/1367045.1367055

Multi-Vdd is an effective method to reduce both leakage and dynamic power. A key challenge in a multi-Vdd design is to control the complexity of the power-supply system and limit the demand for level shifters. This can be tackled by grouping cells...

Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
Nicola Bombieri, Franco Fummi, Graziano Pravadelli
Article No.: 47
DOI: 10.1145/1367045.1367056

In transaction-level modeling (TLM), verification methodologies based on transactions allow testbenches, properties, and IP cores in mixed TL-RTL designs to be reused. However, no papers in the literature analyze the effectiveness of...

Processor virtualization for secure mobile terminals
Hiroaki Inoue, Junji Sakai, Masato Edahiro
Article No.: 48
DOI: 10.1145/1367045.1367057

We propose a processor virtualization architecture, VIRTUS, to provide a dedicated domain for preinstalled applications and virtualized domains for downloaded native applications. With it, security-oriented next-generation mobile terminals can...

Combining system scenarios and configurable memories to tolerate unpredictability
Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor
Article No.: 49
DOI: 10.1145/1367045.1367058

Process variability and the dynamism of new applications increase the uncertainty of embedded systems and force designers to use pessimistic assumptions, which have a tremendous impact on both the performance and energy consumption of their memory...

ILP-Based energy minimization techniques for banked memories
Ozcan Ozturk, Mahmut Kandemir
Article No.: 50
DOI: 10.1145/1367045.1367059

Main memories can consume a significant portion of overall energy in many data-intensive embedded applications. One way of reducing this energy consumption is banking, that is, dividing available memory space into multiple banks and placing unused...

Resource sharing among mutually exclusive sum-of-product blocks for area reduction
Sabyasachi Das, Sunil P. Khatri
Article No.: 51
DOI: 10.1145/1367045.1367060

In state-of-the-art digital designs, arithmetic blocks consume a major portion of the total area of the IC. The arithmetic sum-of-product (SOP) is the most widely used arithmetic block. Some of the examples of SOP are adder, subtractor,...

Partitioning parameterized 45-degree polygons with constraint programming
I-Lun Tseng, Adam Postula
Article No.: 52
DOI: 10.1145/1367045.1367061

An algorithm for partitioning parameterized 45-degree polygons into parameterized trapezoids is proposed in this article. The algorithm is based on the plane-sweep technique and can handle polygons with complicated constraints. The input to the...

Power-aware SoC test planning for effective utilization of port-scalable testers
Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Article No.: 53
DOI: 10.1145/1367045.1367062

Many system-on-chip (SoC) integrated circuits contain embedded cores with different scan frequencies. To better meet the test requirements for such heterogeneous SoCs, leading tester companies have recently introduced port-scalable testers, which...

Evolution of synthetic RTL benchmark circuits with predefined testability
Tomas Pecenka, Lukas Sekanina, Zdenek Kotasek
Article No.: 54
DOI: 10.1145/1367045.1367063

This article presents a new real-world application of evolutionary computing in the area of digital-circuits testing. A method is described which enables to evolve large synthetic RTL benchmark circuits with a predefined structure and testability....