Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14 Issue 1, January 2009

SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications
Joachim Keinert, Martin Streub&uhorbar;hr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, J&uhorbar;rgen Teich, Michael Meredith
Article No.: 1
DOI: 10.1145/1455229.1455230

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate...

CoMPSoC: A template for composable and predictable multi-processor system on chips
Andreas Hansson, Kees Goossens, Marco Bekooij, Jos Huisken
Article No.: 2
DOI: 10.1145/1455229.1455231

A growing number of applications, often with firm or soft real-time requirements, are integrated on the same System on Chip, in the form of either hardware or software intellectual property. The applications are started and stopped at run time,...

System-scenario-based design of dynamic embedded systems
Stefan Valentin Gheorghita, Martin Palkovic, Juan Hamers, Arnout Vandecappelle, Stelios Mamagkakis, Twan Basten, Lieven Eeckhout, Henk Corporaal, Francky Catthoor, Frederik Vandeputte, Koen De Bosschere
Article No.: 3
DOI: 10.1145/1455229.1455232

In the past decade, real-time embedded systems have become much more complex due to the introduction of a lot of new functionality in one application, and due to running multiple applications concurrently. This increases the dynamic nature of...

SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects
Qiang Xu, Yubin Zhang, Krishnendu Chakrabarty
Article No.: 4
DOI: 10.1145/1455229.1455233

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-on-a-chip (SOC) has mainly focused on minimizing the...

A gateway node with duty-cycled radio and processing subsystems for wireless sensor networks
Zhong-Yi Jin, Curt Schurgers, Rajesh K. Gupta
Article No.: 5
DOI: 10.1145/1455229.1455234

Wireless sensor nodes are increasingly being tasked with computation and communication intensive functions while still subject to constraints related to energy availability. On these embedded platforms, once all low power design techniques have...

An energy-efficient I/O request mechanism for multi-bank flash-memory storage systems
Chin-Hsien Wu
Article No.: 6
DOI: 10.1145/1455229.1455235

Emerging critical issues for flash-memory storage systems, especially with regard to implementation within many embedded systems, are the programmed I/O nature of data transfers and their energy-efficient nature. We propose an I/O request...

A design automation and power estimation flow for RFID systems
Swapna Dontharaju, Shenchih Tung, James T. Cain, Leonid Mats, Marlin H. Mickle, Alex K. Jones
Article No.: 7
DOI: 10.1145/1455229.1455236

While RFID has become a ubiquitous technology, there is still a need for RFID systems with different capabilities, protocols, and features depending on the application. This article describes a design automation flow and power estimation technique...

Provably efficient algorithms for resolving temporal and spatial difference constraint violations
Ali Dasdan
Article No.: 8
DOI: 10.1145/1455229.1455237

A system of difference constraints is a formal model of temporal and spatial constraints in many areas such as scheduling, constraint satisfaction, and layout compaction. During construction of such a system, constraint violations often arise, and...

Design intent coverage revisited
Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das, Prasenjit Basu, P. P. Chakrabarti
Article No.: 9
DOI: 10.1145/1455229.1455238

Design intent coverage is a formal methodology for analyzing the gap between a formal architectural specification of a design and the formal functional specifications of the component RTL blocks of the design. In this article we extend the...

Model checking sequential software programs via mixed symbolic analysis
Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivančić
Article No.: 10
DOI: 10.1145/1455229.1455239

We present an efficient symbolic search algorithm for software model checking. Our algorithms perform word-level reasoning by using a combination of decision procedures in Boolean and integer and real domains, and use novel symbolic search...

Interconnect customization for a hardware fabric
Gayatri Mehta, Justin Stander, Mustafa Baz, Brady Hunsaker, Alex K. Jones
Article No.: 11
DOI: 10.1145/1455229.1455240

This article describes several multiplexer-based interconnection strategies designed to improve energy consumption of stripe-based coarse-grain reconfigurable fabrics. Application requirements for the architecture as well as two dense subgraphs...

Congestion prediction in early stages of physical design
Chiu-Wing Sham, Evangeline F. Y. Young, Jingwei Lu
Article No.: 12
DOI: 10.1145/1455229.1455241

Routability optimization has become a major concern in physical design of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominant factor of the overall performance of a circuit. In order to optimize...

Energy and switch area optimizations for FPGA global routing architectures
Yi Zhu, Yuanfang Hu, Michael B. Taylor, Chung-Kuan Cheng
Article No.: 13
DOI: 10.1145/1455229.1455242

Low energy and small switch area usage are two important design objectives in FPGA global routing architecture design. This article presents an improved MCF model based CAD flow that performs aggressive optimizations, such as topology and wire...

Opposite-phase register switching for peak current minimization
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
Article No.: 14
DOI: 10.1145/1455229.1455243

In a synchronous sequential circuit, huge current peaks are often observed at the moment of clock transition (since all registers are clocked). Previous works focus on reducing the number of switching registers. However, even though the switching...

Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2
Yen-Chun Lin, Li-Ling Hung
Article No.: 15
DOI: 10.1145/1455229.1455244

Prefix computation is used in various areas and is considered as a primitive operation. Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. The depth of a prefix circuit is a measure of its processing time;...

Lens aberration aware placement for timing yield
Andrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang
Article No.: 16
DOI: 10.1145/1455229.1455245

Process variations due to lens aberrations are to a large extent systematic, and can be modeled for purposes of analyses and optimizations in the design phase. Traditionally, variations induced by lens aberrations have been considered random due...

A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications
Chih-Da Chien, Cheng-An Chien, Jui-Chin Chu, Jiun-In Guo, Ching-Hwa Cheng
Article No.: 17
DOI: 10.1145/1455229.1455246

This article proposes a low-cost, low-power multistandard video decoder for high definition (HD) video applications. The proposed design supports multiple-standard (JPEG baseline, MPEG-1/2/4 Simple Profile (SP), and H.264 Baseline Profile (BP))...

Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS
Pedro Reviriego, Juan Antonio Maestro
Article No.: 18
DOI: 10.1145/1455229.1455247

Memories are one of the most widely used elements in electronic systems, and their reliability when exposed to Single Events Upsets (SEUs) has been studied extensively. As transistor sizes shrink, Multiple Bits Upsets (MBUs) are becoming an...