Design Automation of Electronic Systems (TODAES)


Search Issue
enter search term and/or author name


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14 Issue 4, August 2009

2009 ACM TODAES best paper award: Optimization of polynomial datapaths using finite ring algebra
Sivaram Gopalakrishnan, Priyank Kalla
Article No.: 47
DOI: 10.1145/1562514.1562515

Efficient memory management for hardware accelerated Java Virtual Machines
Peter Bertels, Wim Heirman, Erik D'Hollander, Dirk Stroobandt
Article No.: 48
DOI: 10.1145/1562514.1562516

Application-specific hardware accelerators can significantly improve a system's performance. In a Java-based system, we then have to consider a hybrid architecture that consists of a Java Virtual Machine running on a general-purpose processor...

A hardware platform for efficient worm outbreak detection
Miad Faezipour, Mehrdad Nourani, Rina Panigrahy
Article No.: 49
DOI: 10.1145/1562514.1562517

Network Intrusion Detection Systems (NIDS) monitor network traffic to detect attacks or unauthorized activities. Traditional NIDSes search for patterns that match typical network compromise or remote hacking attempts. However, newer networking...

Thermal sensor allocation and placement for reconfigurable systems
Byunghyun Lee, Ki-Seok Chung, Bontae Koo, Nak-Woong Eum, Taewhan Kim
Article No.: 50
DOI: 10.1145/1562514.1562518

A dynamic monitoring of thermal behavior of hardware resources using thermal sensors is very important to maintain the operation of systems safe and reliable. This article addresses the problem of thermal sensor allocation and placement for...

T-trees: A tree-based representation for temporal and three-dimensional floorplanning
Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang
Article No.: 51
DOI: 10.1145/1562514.1562519

Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this article, we model each task as a 3D-box and deal with the temporal floorplanning/placement...

Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin
Article No.: 52
DOI: 10.1145/1562514.1562520

As technology continues to shrink, reducing leakage power of Field-Programmable Gate Arrays (FPGAs) becomes a critical issue for the practical use of FPGAs. In this article, we address the leakage issue of partially dynamically reconfigurable FPGA...

Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
Po-Yuan Chen, Chiao-Chen Fang, Tingting Hwang, Hsi-Pin Ma
Article No.: 53
DOI: 10.1145/1562514.1562521

In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As scaling progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle the...

Variation-aware multimetric optimization during gate sizing
Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam
Article No.: 54
DOI: 10.1145/1562514.1562522

The aggressive scaling of technology has not only accentuated the effects of intradie parametric variations in devices, but it has also impacted the effects of optimizing a certain performance metric on the optimality of other metrics. Thus, there...

Power-delay optimization in VLSI microprocessors by wire spacing
Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer
Article No.: 55
DOI: 10.1145/1562514.1562523

The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted Power-Delay Sum (WPDS)...

SUPERB: Simulator utilizing parallel evaluation of resistive bridges
Piet Engelke, Bernd Becker, Michel Renovell, Juergen Schloeffel, Bettina Braitling, Ilia Polian
Article No.: 56
DOI: 10.1145/1562514.1596831

A high-performance resistive bridging fault simulator SUPERB (Simulator Utilizing Parallel Evaluation of Resistive Bridges) is proposed. It is based on fault sectioning in combination with parallel-pattern or parallel-fault multiple-stuck-at...