Design Automation of Electronic Systems (TODAES)


Search Issue
enter search term and/or author name


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16 Issue 2, March 2011

Call for papers: Verification issue and challenges with multicore systems
Massoud Pedram
Article No.: 12
DOI: 10.1145/1929943.1929944

Dimension-reducible Boolean functions based on affine spaces
Anna Bernasconi, Valentina Ciriani
Article No.: 13
DOI: 10.1145/1929943.1929945

We define and study a new class of regular Boolean functions called D-reducible. A D-reducible function, depending on all its n input variables, can be studied and synthesized in a space of dimension strictly smaller than n. We show...

Overhead-aware energy optimization for real-time streaming applications on multiprocessor System-on-Chip
Yi Wang, Hui Liu, Duo Liu, Zhiwei Qin, Zili Shao, Edwin H.-M. Sha
Article No.: 14
DOI: 10.1145/1929943.1929946

In this article, we focus on solving the energy optimization problem for real-time streaming applications on multiprocessor System-on-Chip by combining task-level coarse-grained software pipelining with DVS (Dynamic Voltage Scaling) and DPM...

Automatic memory partitioning and scheduling for throughput and power optimization
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
Article No.: 15
DOI: 10.1145/1929943.1929947

Memory bottleneck has become a limiting factor in satisfying the explosive demands on performance and cost in modern embedded system design. Selected computation kernels for acceleration are usually captured by nest loops, which are optimized by...

MicroFix: Using timing interpolation and delay sensors for power reduction
Guihai Yan, Yinhe Han, Hui Liu, Xiaoyao Liang, Xiaowei Li
Article No.: 16
DOI: 10.1145/1929943.1929948

Traditional DVFS schemes are oblivious to fine-grained adaptability resulting from path-grained timing imbalance. With the awareness of such fine-grained adaptability, better power-performance efficiency can be obtained. We propose a new scheme,...

Reducing the switching activity of test sequences under transparent-scan
Irith Pomeranz, Sudhakar M. Reddy
Article No.: 17
DOI: 10.1145/1929943.1929949

Transparent-scan is a test application scheme for scan circuits. It provides unique opportunities for test compaction that do not exist with the standard test application scheme. We show that it also provides unique opportunities for reducing the...

A parallel branch-and-cut approach for detailed placement
Stephen Cauley, Venkataramanan Balakrishnan, Y. Charlie Hu, Cheng-Kok Koh
Article No.: 18
DOI: 10.1145/1929943.1929950

We introduce a technique that utilizes distributing computing resources for the efficient optimization of a traditional physical design problem. Specifically, we present a detailed placement strategy designed to exploit distributed computing...

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment
Yih-Lang Li, Yu-Ning Chang, Wen-Nai Cheng
Article No.: 19
DOI: 10.1145/1929943.1929951

Track assignment, which is an intermediate stage between global routing and detailed routing, provides a good platform for promoting performance, and for imposing additional constraints during routing, such as crosstalk. Gridless track assignment...

Scan-based attacks on linear feedback shift register based stream ciphers
Yu Liu, Kaijie Wu, Ramesh Karri
Article No.: 20
DOI: 10.1145/1929943.1929952

Stream cipher is an important class of encryption algorithm that encrypts plaintext messages one bit at a time. Various stream ciphers are deployed in wireless telecommunication applications because they have simple hardware circuitry, are...