Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 16 Issue 4, October 2011

2011 ACM TODAES best paper award
Meikang Qiu, Edwin H.-M. Sha
Article No.: 36
DOI: 10.1145/2003695.2003696

In high-level synthesis for real-time embedded systems using heterogeneous functional units (FUs), it is critical to select the best FU type for each task. However, some tasks may not have fixed execution times. This article models each varied...

Concurrency-oriented verification and coverage of system-level designs
Alper Sen
Article No.: 37
DOI: 10.1145/2003695.2003697

Correct concurrent System-on-Chips (SoCs) are very hard to design and reason about. In this work, we develop an automated framework complete with concurrency-oriented verification and coverage techniques for system-level designs. Our techniques...

A probabilistic analysis of coverage methods
Laurent Fournier, Avi Ziv, Ekaterina Kutsy, Ofer Strichman
Article No.: 38
DOI: 10.1145/2003695.2003698

Coverage is an important measure for the quality and completeness of the functional verification of hardware logic designs. Verification teams spend a significant amount of time looking for bugs in the design and in providing high-quality...

GALS-Designer: A design framework for GALS software systems
Wei-Tsun Sun, Zoran Salcic
Article No.: 39
DOI: 10.1145/2003695.2003699

GALS-Designer is a framework for the design of software systems which comply with the formal Globally Asynchronous Locally Synchronous model of computation (GALS). Those systems consist of single or multiple GALS programs and their immediate...

Timing variation-aware scheduling and resource binding in high-level synthesis
Kartikey Mittal, Arpit Joshi, Madhu Mutyam
Article No.: 40
DOI: 10.1145/2003695.2003700

Due to technological scaling, process variations have increased significantly, resulting in large variations in the delay of the functional units. Hence, the worst-case approach is becoming increasingly pessimistic in meeting a certain performance...

Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs
Xiaofang Wang, Pallav Gupta
Article No.: 41
DOI: 10.1145/2003695.2003701

Although state-of-the-art field-programmable gate arrays offer exciting new opportunities in exploring low-cost high-performance architectures for data-intensive scientific applications, they also present serious challenges....

Memory access optimization in compilation for coarse-grained reconfigurable architectures
Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Yunheung Paek
Article No.: 42
DOI: 10.1145/2003695.2003702

Coarse-grained reconfigurable architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and moving the complexity to application mapping. One major challenge comes...

Dynamic data folding with parameterizable FPGA configurations
Karel Bruneel, Wim Heirman, Dirk Stroobandt
Article No.: 43
DOI: 10.1145/2003695.2003703

In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter...

Parallel circuit simulation with adaptively controlled projective integration
Wei Dong, Peng Li
Article No.: 44
DOI: 10.1145/2003695.2003704

In this article, a parallel transient circuit simulation approach based on an adaptively-controlled time-stepping scheme is proposed. Different from the widely-used implicit numerical integration techniques in most transient simulators, this work...

Mitigating the effects of large multiple cell upsets (MCUs) in memories
Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shijie Wen, Richard Wong
Article No.: 45
DOI: 10.1145/2003695.2003705

Reliability is a critical issue for memories. Radiation particles that hit the device can cause errors in some cells, which can lead to data corruption. To avoid this problem, memories are protected with per-word error correction codes (ECCs)....

Integrated microarchitectural floorplanning and run-time controller for inductive noise mitigation
Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim
Article No.: 46
DOI: 10.1145/2003695.2003706

In this article, we propose a design methodology using two complementary techniques to address high-frequency inductive noise in the early design phase of a microprocessor. First, we propose a noise-aware floorplanning technique that uses...

IO connection assignment and RDL routing for flip-chip designs
Jin-Tai Yan
Article No.: 47
DOI: 10.1145/2003695.2003707

Given a set of IO buffers and a set of bump balls with the capacity constraints between two adjacent bump balls, based on the construction of the Delaunary triangulation and a Manhattan Voronoi diagram, an O(n2) assignment...

Clock Tree synthesis for TSV-based 3D IC designs
Tak-Yung Kim, Taewhan Kim
Article No.: 48
DOI: 10.1145/2003695.2003708

For the cost-effective implementation of clock trees in through-silicon via (TSV)-based 3D IC designs, we propose core algorithms for 3D clock tree synthesis. For a given abstract tree topology, we propose DLE-3D (&dlowbar;eferred &llowbar;ayer...

Clock buffer polarity assignment with skew tuning
Jianchao Lu, Baris Taskin
Article No.: 49
DOI: 10.1145/2003695.2003709

A clock polarity assignment method is proposed that reduces the peak current on the vdd/gnd rails of an integrated circuit. The impacts of (i) the output capacitive load on the peak current drawn by the sink-level clock buffers, and (ii) the...

Analog layout retargeting using geometric programming
Shaoxi Wang, Xinzhang Jia, Arthur B. Yeh, Lihong Zhang
Article No.: 50
DOI: 10.1145/2003695.2003710

To satisfy the requirements of complex and special analog layout constraints, a new analog layout retargeting method is presented in this article. Our approach uses geometric programming (GP) to achieve new technology design rules, implement...

A 36μW heartbeat-detection processor for a wireless sensor node
Filipa Duarte, Jos Hulzink, Jun Zhou, Jan Stuijt, Jos Huisken, Harmke De Groot
Article No.: 51
DOI: 10.1145/2003695.2003711

In order to provide better services to elderly people, home healthcare monitoring systems have been increasingly deployed. Typically, these systems are based on wireless sensor nodes, and should utilize very low energy during their lifetimes, as...