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An Extended SystemC Framework for Efficient HW/SW Co-Simulation
Meng-Huan Wu, Peng-Chih Wang, Cheng-Yang Fu, Ren-Song Tsay
Article No.: 11
In this article, we propose an extended SystemC framework that directly enables software simulation in SystemC. Although SystemC has been widely adopted for system-level simulation of hardware designs nowadays, to complete HW/SW co-simulation, it...
Optimized 3D Network-on-Chip Design Using Simulated Allocation
Pingqiang Zhou, Ping-Hung Yuh, Sachin S. Sapatnekar
Article No.: 12
Three-dimensional (3D) silicon integration technologies have provided new opportunities for Network-on-Chip (NoC) architecture design in Systems-on-Chip (SoCs). In this article, we consider the application-specific NoC architecture design problem...
Performance/Thermal-Aware Design of 3D-Stacked L2 Caches for CMPs
Guangyu Sun, Huazhong Yang, Yuan Xie
Article No.: 13
Three-dimensional (3D) stacking technology enables integration of more memory on top of chip multiprocessors (CMPs). As the number of cores and the capacity of on-chip memory increase, the Non-Uniform Cache Architecture (NUCA) becomes more...
Timing Analysis of System Initialization and Crash Recovery for a Segment-Based Flash Translation Layer
Chin-Hsien Wu, Hsin-Hung Lin
Article No.: 14
Recently, the capacity of flash-memory storage systems has grown rapidly, and flash-memory technology has advanced along with the wave of consumer electronics and embedded systems. In order to properly manage product cost and initialization...
Computer Generation of Hardware for Linear Digital Signal Processing Transforms
Peter Milder, Franz Franchetti, James C. Hoe, Markus Püschel
Article No.: 15
Linear signal transforms such as the discrete Fourier transform (DFT) are very widely used in digital signal processing and other domains. Due to high performance or efficiency requirements, these transforms are often implemented in hardware. This...
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang
Article No.: 16
Clock gating is a popular technique for reducing power dissipation. In a circuit with clock gating, the clock signal can be shut off without changing the functionality under certain clock-gating conditions. In this article, we observe that the...
A Yield and Reliability Improvement Methodology Based on Logic Redundant Repair with a Repairable Scan Flip-Flop Designed by Push Rule
Masanori Kurimoto, Jun Matsushima, Shigeki Ohbayashi, Yoshiaki Fukui, Michio Komoda, Nobuhiro Tsuda
Article No.: 17
We propose a yield improvement methodology which repairs a faulty chip due to logic defect by using a repairable scan flip-flop (R-SFF). Our methodology improves area penalty, which is a large issue for logic repair technology in actual products,...
Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing
Dong Xiang, Zhen Chen, Laung-Terng Wang
Article No.: 18
Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame...