Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 20 Issue 2, February 2015

ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method
Jingwei Lu, Pengwen Chen, Chin-Chih Chang, Lu Sha, Dennis Jen-Hsin Huang, Chin-Chi Teng, Chung-Kuan Cheng
Article No.: 17
DOI: 10.1145/2699873

We develop a flat, analytic, and nonlinear placement algorithm, ePlace, which is more effective, generalized, simpler, and faster than previous works. Based on the analogy between placement instance and electrostatic system, we develop a...

Robust Design Space Modeling
Qi Guo, Tianshi Chen, Zhi-Hua Zhou, Olivier Temam, Ling Li, Depei Qian, Yunji Chen
Article No.: 18
DOI: 10.1145/2668118

Architectural design spaces of microprocessors are often exponentially large with respect to the pending processor parameters. To avoid simulating all configurations in the design space, machine learning and statistical techniques have been...

Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching
Mottaqiallah Taouil, Said Hamdioui, Erik Jan Marinissen
Article No.: 19
DOI: 10.1145/2699832

Three-Dimensional Stacked IC (3D-SIC) using Through-Silicion Vias (TSVs) is an emerging technology that provides heterogeneous integration, higher performance, and lower power consumption compared to traditional ICs. Stacking 3D-SICs using...

Conditional Diagnosability of Cayley Graphs Generated by Transposition Trees under the PMC Model
Naiwen Chang, Eddie Cheng, Sunyuan Hsieh
Article No.: 20
DOI: 10.1145/2699854

Processor fault diagnosis has played an essential role in measuring the reliability of a multiprocessor system. The diagnosability of many well-known multiprocessor systems has been widely investigated. Conditional diagnosability is a novel...

Data-Driven Optimization of Order Admission Policies in a Digital Print Factory
Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto
Article No.: 21
DOI: 10.1145/2699836

On-demand digital print service is an example of a real-time embedded enterprise system. It offers mass customization and exemplifies personalized manufacturing services. Once a print order is submitted to the print factory by a client, the print...

The Design and Experiments of A SID-Based Power-Aware Simulator for Embedded Multicore Systems
Cheng-Yen Lin, Chung-Wen Huang, Chi-Bang Kuan, Shi-Yu Huang, Jenq-Kuen Lee
Article No.: 22
DOI: 10.1145/2699834

Embedded multicore systems are playing increasingly important roles in the design of consumer electronics. The objective of such systems is to optimize both performance and power characteristics of mobile devices. However, currently there are no...

Prolonging Lifetime of PCM-Based Main Memories through On-Demand Page Pairing
Marjan Asadinia, Mohammad Arjomand, Hamid Sarbazi Azad
Article No.: 23
DOI: 10.1145/2699867

With current memory scalability challenges, Phase-Change Memory (PCM) is viewed as an attractive replacement to DRAM. The preliminary concern for PCM applicability is its limited write endurance that results in fast wear-out of memory cells....

Obstacle-Avoiding Algorithm in X-Architecture Based on Discrete Particle Swarm Optimization for VLSI Design
Xing Huang, Genggeng Liu, Wenzhong Guo, Yuzhen Niu, Guolong Chen
Article No.: 24
DOI: 10.1145/2699862

Obstacle-avoiding Steiner minimal tree (OASMT) construction has become a focus problem in the physical design of modern very large-scale integration (VLSI) chips. In this article, an effective algorithm is presented to construct an OASMT based on...

Marching-Based Wear-Leveling for PCM-Based Storage Systems
Hung-Sheng Chang, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo, Hsiang-Pang Li
Article No.: 25
DOI: 10.1145/2699831

Improving the performance of storage systems without losing the reliability and sanity/integrity of file systems is a major issue in storage system designs. In contrast to existing storage architectures, we consider a PCM-based storage...

Applying Pay-Burst-Only-Once Principle for Periodic Power Management in Hard Real-Time Pipelined Multiprocessor Systems
Gang Chen, Kai Huang, Christian Buckl, Alois Knoll
Article No.: 26
DOI: 10.1145/2699865

Pipelined computing is a promising paradigm for embedded system design. Designing a power management policy to reduce the power consumption of a pipelined system with nondeterministic workload is, however, nontrivial. In this article, we study the...

ASP-Based Encoding Model of Architecture Synthesis for Smart Cameras in Distributed Networks
Franck Yonga, Michael Mefenza, Christophe Bobda
Article No.: 27
DOI: 10.1145/2701419

A synthesis approach based on Answer Set Programming (ASP) for heterogeneous system-on-chips to be used in distributed camera networks is presented. In such networks, the tight resource limitations represent a major challenge for application...

Automated Iterative Pipelining for ASIC Design
Lok-Won Kim, Dong-U Lee, John Villasenor
Article No.: 28
DOI: 10.1145/2660768

We describe an automated pipelining approach for optimally balanced pipeline implementation that achieves low area cost as well as meeting timing requirements. Most previous automatic pipelining methods have focused on Instruction Set Architecture...

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences
Irith Pomeranz
Article No.: 29
DOI: 10.1145/2699853

A class of static test compaction procedures for functional test sequences is based on the omission of unnecessary test vectors. According to the definition used by these procedures, a test vector is unnecessary if all the target faults continue...

Reconfigurable Scan Networks: Modeling, Verification, and Optimal Pattern Generation
Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich
Article No.: 30
DOI: 10.1145/2699863

Efficient access to on-chip instrumentation is a key requirement for post-silicon validation, test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by, for example, IEEE Std 1687-2014 and IEEE Std 1149.1-2013, emerge as an...

A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters
Kamel Beznia, Ahcene Bounceur, Reinhardt Euler, Salvador Mir
Article No.: 31
DOI: 10.1145/2699837

Testing analog integrated circuits is expensive in terms of both test equipment and time. To reduce the cost, Design-For-Test techniques (DFT) such as Built-In Self-Test (BIST) have been developed. For a given Circuit Under Test (CUT), the choice...

A Fault-Aware Toolchain Approach for FPGA Fault Tolerance
Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones
Article No.: 32
DOI: 10.1145/2699838

As the size and density of silicon chips continue to increase, maintaining acceptable manufacturing yields has become increasingly difficult. Recent works suggest that lithography techniques are reaching their limits with respect to enabling high...

Reconfigurable Binding against FPGA Replay Attacks
Jiliang Zhang, Yaping Lin, Gang Qu
Article No.: 33
DOI: 10.1145/2699833

The FPGA replay attack, where an attacker downgrades an FPGA-based system to the previous version with known vulnerabilities, has become a serious security and privacy concern for FPGA design. Current FPGA intellectual property (IP) protection...