Design Automation of Electronic Systems (TODAES)


Search Issue
enter search term and/or author name


ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 3 Issue 2, April 1998

ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems
Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen
Pages: 109-135
DOI: 10.1145/290833.290834
The design of multiprocessor architectures differs from uniprocessor systems in that the number of processors and their interconnection must be considered. This leads to an enormous increase in the design-space exploration time, which is...

Code generation for fixed-point DSPs
Guido Araujo, Sharad Malik
Pages: 136-161
DOI: 10.1145/290833.290837
This paper examines the problem of code-generation for Digital Signal Processors (DSPs). We make two major contributions. First, for an important class of DSP architectures, we propose an optimal O(n) algorithm for the tasks of...

Estimation of lower bounds in scheduling algorithms for high-level synthesis
Giri Tiruvuri, Moon Chung
Pages: 162-180
DOI: 10.1145/290833.290839
To produce efficient design, a high-level synthesis system should be able to analyze a variety of cost-performance tradeoffs. The system can use lower-bound performance estimated methods to identify and puune inferior designs without producint...

Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu
Pages: 181-208
DOI: 10.1145/290833.290841
Incorporating functional partitioning into a synthesis methodology leads to several important advantages. In functional partitioning, we first partition a functional specification into smaller subspecifications and then synthesize structure for...

Breakpoints and breakpoint detection in source-level emulation
Gernot H. Koch, W. Rosenstiel, U. Kebschull
Pages: 209-230
DOI: 10.1145/290833.290843
We present an approach for accelerating the validation speed of behavioral system descriptions through hardware emulation. The method allows source-level debuggingof running hardware specified in behavioral VH DL in a way similar to sorce-leve...

Functional test generation for delay faults in combinational circuits
Irith Pomeranz, Sudhakar M. Reddy
Pages: 231-248
DOI: 10.1145/290833.290845
We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the...

Structural diagnosis of interconnects by coloring
X. T. Chen, F. J. Meyer, F. Lombardi
Pages: 249-271
DOI: 10.1145/290833.290848
This paper presents a new approach for diagnosing shorts in interconnects in which the adjacencies between nets are known. This structural approach exploits different graph coloring techniques to generate a test set with no aliasing and...

Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
Dinesh P. Mehta
Pages: 272-284
DOI: 10.1145/290833.290850
This paper proposes a technique for estimating the storage requirements of the Rectangular Corner Stitching (RCS) data structure [Ousterhout 1984] and the L-shaped Corner Stitching (LCS) data structure [Mehta and Blust 1997] on a given circuit...

Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization
Subhrajit Bhattacharya, Sujit Dey, Franc Breglez
Pages: 285-307
DOI: 10.1145/290833.290852
This paper analyzes the effect of resource sharing and assignment on the clock period of the synthesized circuit. The assignment phase assigns or binds operations of the scheduled behavioral description to a set of allocated resources. We focus...