Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 3 Issue 3, July 1998

Auxiliary variables for BDD-based representation and manipulation of Boolean functions
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
Pages: 309-340
DOI: 10.1145/293625.293626
BDDs are the state-of-the-art technique for representing and manipulating Boolean functions. Their introduction caused a major leap forward in synthesis, verification, and testing. However, they are often unmanageable because of the large amount...

Bounded-skew clock and Steiner routing
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, C.-W. Albert Tsao
Pages: 341-388
DOI: 10.1145/293625.293628
We study the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models. This problem captures several engineering tradeoffs in the design of routing topologies with controlled skew. Our bounded-skew...

Confidence analysis for defect-level estimation of VLSI random testing
Wen-Ben Jone, K. S. Tsai
Pages: 389-407
DOI: 10.1145/293625.293629
The defect level in circuit testing is the percentage of circuits such as chips, that are defective and shipped for use after testing. Our previously published results showed that the defect level of circuit fabrication and testing should be a...

Rate analysis for embedded systems
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
Pages: 408-436
DOI: 10.1145/293625.293631
Embedded systems consist of interacting components that are required to deliver a specific functionality under constraints on execution rates and relative time separation of the components. In this article, we model an embedded system using...

Optimal clock period FPGA technology mapping for sequential circuits
Peichen Pan, C. L. Liu
Pages: 437-462
DOI: 10.1145/293625.293632
We study the technology mapping problem for sequential circuits for look-up table (LUT) based field programmable gate arrays (FPGAs). Existing approaches to the problem simply remove the flip-flops (FFs), then map the remaining combinational...

The edge-based design rule model revisited
Michael A. Riepe, Karem A. Sakallah
Pages: 463-486
DOI: 10.1145/293625.293633
A model for integrated circuit design rules based on rectangle edge constraints has been proposed by Jeppson, Christensson, and Hedenstierna. This model appears to be the most rigorous proposed to date for the description of such edge-based...

Eliminating false loops caused by sharing in control path
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
Pages: 487-495
DOI: 10.1145/293625.293635
In high-level synthesis, resource sharing may result in a circuit containing false loops that create great difficulty in timing validation during the design sign-off phase. It is hence desirable to avoid generating any false loops in a...

Optimal river routing with crosstalk constraints
Hai Zhou, D. F. Wong
Pages: 496-514
DOI: 10.1145/293625.293636
With the increasing density of VLSI circuits, the interconnection wires are being packed even closer. This has increased the effect of interaction among these wires on circuit performance and hence, the importance of controlling crosstalk. In...