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Introduction to the Special Section on Advances in Physical Design Automation
Chris Chu, Mustafa Ozdal
Article No.: 41
Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured...
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints
Nima Karimpour Darav, Ismail S. Bustany, Andrew Kennings, David Westwick, Laleh Behjat
Article No.: 43
The legalization step is performed after global placement where wire length and routability are optimized or during timing optimization where buffer insertion or gate sizing are applied to meet timing requirements. Therefore, an ideal legalization...
Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit
Chen Wang, Yanan Sun, Shiyan Hu, Li Jiang, Weikang Qian
Article No.: 44
As the conventional silicon-based CMOS technology marches toward the sub-10nm region, the problem of high power density becomes increasingly serious. Under this circumstance, the carbon-nanotube field effect transistors (CNFETs) emerge as a...
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction
Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin
Article No.: 45
Owing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches for the multilayer obstacle-avoiding rectilinear...
Ordered Escape Routing with Consideration of Differential Pair and Blockage
Fengxian Jiao, Sheqin Dong
Article No.: 46
Ordered escape routing is a critical issue in high-speed PCB routing. Differential pair and thermal-blockage-avoided are useful in PCB design to obtain high noise immunity and low electromagnetic interference. In this article, a Min-cost...
Routable and Matched Layout Styles for Analog Module Generation
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
Article No.: 47
Two1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid method for capacitor arrays—are introduced. Based on the proposed layout styles and...
iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis
Pei-Yu Lee, Iris Hui-Ru Jiang
Article No.: 48
As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical...
Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid
Sayed Abdullah Sadat, Mustafa Canbolat, Selçuk Köse
Article No.: 49
Parallel on-chip voltage regulation, where multiple regulators are connected to the same power grid, has recently attracted significant attention with the proliferation of small on-chip voltage regulators. In this article, the number, size, and...
Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs
Burcin Cakir, Sharad Malik
Article No.: 50
Outsourcing of design and manufacturing processes makes integrated circuits (ICs) vulnerable to adversarial changes and raises concerns about their integrity. Reverse engineering the manufactured netlist helps identify malicious insertions. In...
An Integration Flow for Mixed-Critical Embedded Systems on a Flexible Time-Triggered Platform
Philipp Ittershagen, Kim Grüttner, Wolfgang Nebel
Article No.: 51
The rise of mixed-critical embedded systems imposes novel challenges on the specification, development, and functional validation in a design flow. In the emerging dynamic scheduling context of mixed-criticality platforms, the system behaviour...
Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption
Article No.: 52
Logic encryption is an IC protection technique for preventing an IC design from overproduction and unauthorized use. It hides a design’s functionality by inserting key gates and key inputs, such that a secret key is required to activate...
Partially Invariant Patterns for LFSR-Based Generation of Close-to-Functional Broadside Tests
Article No.: 53
Close-to-functional scan-based tests are expected to create close-to-functional operation conditions in order to avoid overtesting of delay faults. Existing metrics for the proximity to functional operation conditions are based on the scan-in...
Thermal-Sensor-Based Occupancy Detection for Smart Buildings Using Machine-Learning Methods
Hengyang Zhao, Qi Hua, Hai-Bao Chen, Yaoyao Ye, Hai Wang, Sheldon X.-D. Tan, Esteban Tlelo-Cuautle
Article No.: 54
In this article, we propose a novel approach to detect the occupancy behavior of a building through the temperature and/or possible heat source information. The new method can be used for energy reduction and security monitoring for emerging smart...
Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips
Shalu, Srijan Kumar, Ananya Singla, Sudip Roy, Krishnendu Chakrabarty, Partha P. Chakrabarti, Bhargab B. Bhattacharya
Article No.: 55
Recent studies in algorithmic microfluidics have led to the development of several techniques for automated solution preparation using droplet-based digital microfluidic (DMF) biochips. A major challenge in this direction is to produce a mixture...