Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 5 Issue 3, July 2000

Mary Jane Irwin
Pages: 265-266
DOI: 10.1145/348019.348027

Power optimization of technology-dependent circuits based on symbolic computation of logic implications
R. Iris Bahar, Ernest T. Lampe, Enrico Macii
Pages: 267-293
DOI: 10.1145/348019.348028
This paper presents a novel approach to the problem of optimizing combinational circuits for low power. The method is inspired by the fact that power analysis performed on a technology mapped network gives more realistic estimates than it would...

Allocation of FIFO structures in RTL data paths
M. Balakrishnan, Heman Khanna
Pages: 294-310
DOI: 10.1145/348019.348044
Along with functional units, storage and interconnects contribute significantly to data path costs. This paper addresses the issue of reducing the costs of storage and interconnect. In a post-datapath synthesis phase, one or more queues can be...

Synthesis of low-power selectively-clocked systems from high-level specification
L. Benini, G. De Micheli
Pages: 311-321
DOI: 10.1145/348019.348050
We propose a technique for synthesizing low-power systems from behavioral specifications. We analyze the control flow of the specification model to detect mutually exclusive sections of the computation. A selectively-clocked...

Efficient optimal design space characterization methodologies
Stephen A. Blythe, Robert A. Walker
Pages: 322-336
DOI: 10.1145/348019.348058
One of the primary advantages of a high-level synthesis system is its ability to explore the design space. This paper presents several methodologies for design space exploration that compute all optimal tradeoff points for the...

Regression-based RTL power modeling
Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
Pages: 337-372
DOI: 10.1145/348019.348081
Register-transfer level (RTL) power estimation is a key feature for synthesis-based design flows. The main challenge in establishing a sound RTL power estimation methodology is the construction of accurate, yet efficient, models of the power...

Retiming-based factorization for sequential logic optimization
Surendra Bommu, Niall O'Neill, Maciej Ciesielski
Pages: 373-398
DOI: 10.1145/348019.348068
Current sequential optimization techniques apply a variety of logic transformations that mainly target the combinational logic component of the circuit. Retiming is typically applied as a postprocessing step to the gate-level implementation...

Hardware/software synthesis of formal specifications in codesign of embedded systems
Vincenza Carchiolo, Michele Malgeri, Guiseppe Mangioni
Pages: 399-432
DOI: 10.1145/348019.348093
CoDesign aims to integrate the design techniques of hardware and software. In this work, we present a CoDesign methodology based on a formal approach to embedded system specification. This methodology uses the Templated T-LOTOS language to...

Timing-driven routing for symmetrical array-based FPGAs
Yao-Wen Chang, Kai Zhu, D. F. Wong
Pages: 433-450
DOI: 10.1145/348019.348101
In this paper we present a timing-driven router for symmetrical array-based FPGAs. The routing resources in the FPGAs consist of segments of various lengths. Researchers have shown that the number of segments, instead of wirelength, used by a...

Modeling layout tools to derive forward estimates of area and delay at the RTL level
Donald S. Gelosh, Dorothy E. Steliff
Pages: 451-491
DOI: 10.1145/348019.348148
Forward estimates of area and delay facilitate effective decision-making when searching the solution space of digital designs. Current estimation techniques focus on modeling the layout result and fail to deliver timely or accurate estimates....

A codesign back-end approach for embedded system design
G. Gogniat, M. Auguin, L. Bianco, A. Pegatoquet
Pages: 492-509
DOI: 10.1145/348019.348156
Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one...

CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells
Avaneendra Gupta, John P. Hayes
Pages: 510-547
DOI: 10.1145/348019.348234
A novel technique, CLIP, is presented for the automatic generation of optimal layouts of CMOS cells in the two-dimensional (2D) style. CLIP is based on integer-linear programming...

Dynamic state traversal for sequential circuit test generation
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel
Pages: 548-565
DOI: 10.1145/348019.348288
A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state...

High-level library mapping for memories
Pradip K. Jha, Nikil D. Dutt
Pages: 566-603
DOI: 10.1145/348019.348297
We present high-level library mapping, a technique that synthesizes a source memory module from a library of target memory modules. In this paper, we define the problem of high-level library mapping for memories, identify and solve the three...

Optimizing computations for effective block-processing
Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak
Pages: 604-630
DOI: 10.1145/348019.348304
Block-processing can decrease the time and power required to perform any given computation by simultaneously processing multiple samples of input data. The effectiveness of block-processing can be severely limited, however, if the delays in the...

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults
David E. Long, Mahesh A. Iyer, Miron Abramovici
Pages: 631-657
DOI: 10.1145/348019.348311
In this paper, we first present an algorithm (FILL) to efficiently identify a large subset of illegal states in synchronous sequential circuits, without assuming a global reset mechanism. A second algorithm, FUNI, finds sequentially untestable...

Stochastic sequential machine synthesis with application to constrained sequence generation
Diana Marculescu, Radu Marculescu, Massoud Pedram
Pages: 658-681
DOI: 10.1145/348019.348566
In power estimation, one is faced with two problems: (1) generating input vector sequences that satisfy a given statistical behavior (in terms of signal probabilities and correlations among bits); (2) making these sequences as short as possible...

On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau
Pages: 682-704
DOI: 10.1145/348019.348570
Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on processor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called...

Environment modeling and language universality
Richard Raimi, Ramin Hojati, Kedar S. Namjoshi
Pages: 705-725
DOI: 10.1145/348019.348572
In this paper we outline a theory for the environment-modeling problem, the problem of abstracting component finite state machines (FSMs)bordering a particular FSM of interest within a network of interacting FSMs. The goal is to...

Three-layer bubble-sorting-based nonManhattan channel routing
Jin-Tai Yan
Pages: 726-734
DOI: 10.1145/348019.350285
It is well known that a nonManhattan channel router can use fewer routing tracks, and is never worse than a Manhattan router in a channel. To my knowledge, a three-layer bubble-sorting-based nonManhattan channel routing problem is always solved...

Efficient routability check algorithms for segmented channel routing
Cheng-Hsing Yang, Sao-Jie Chen, Jan-Ming Ho, Chia-Chun Tsai
Pages: 735-747
DOI: 10.1145/348019.348574
The segmented channel-routing problem arises in the context of row-based field programmable gate arrays (FPGAs). Since the K-segment channel-routing problem is NP-complete for K ≥ 2, an efficient algorithm...