Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 7 Issue 1, January 2002

General technology mapping for field-programmable gate arrays based on lookup tables
Amit Chowdhary, John P. Hayes
Pages: 1-32
DOI: 10.1145/504914.504915
We present a general technology-mapping methodology (TULIP) for field-programmable gate arrays (FPGAs) that can yield optimal results, and is applicable to any FPGA with a logic block composed of lookup tables (LUTs). We introduce the concept of a...

ATPG tools for delay faults at the functional level
M. Michael, S. Tragoudas
Pages: 33-57
DOI: 10.1145/504914.504916
We present an ATPG tool for functional delay faults which applies to the single-input transition (SIT) and the multi-input transition (MIT) fault models, and is based on Reduced Ordered Binary Decision Diagrams (ROBDDs). We are able, for the first...

Prefetching for improved bus wrapper performance in cores
Roman Lysecky, Frank Vahid
Pages: 58-90
DOI: 10.1145/504914.504917
Reuse of cores can reduce design time for systems-on-a-chip. Such reuse is dependent on being able to easily interface a core to any bus. To enable such interfacing, many propose separating a core's interface from its internals by using a bus...

Cluster-aware iterative improvement techniques for partitioning large VLSI circuits
Shantanu Dutt, Wenyong Deng
Pages: 91-121
DOI: 10.1145/504914.504918
Move-based iterative improvement partitioning (IIP) methods, such as the Fiduccia-Mattheyses (FM) algorithm [Fidducia and Mattheyses 1982] and Krishnamurthy's Look-Ahead (LA) algorithm [Krishnamurthy 1984], are widely used in VLSI CAD applications,...

Microarchitectural synthesis of performance-constrained, low-power VLSI designs
Laurence Goodby, Alex Orailoğlu, Paul M. Chau
Pages: 122-136
DOI: 10.1145/504914.504919
New portable signal-processing applications such as mobile telephony, wireless computing, and personal digital assistants place stringent power consumption limits on their constituent components. Substantial power savings can be realized if 5 V...

Satisfiability models and algorithms for circuit delay computation
Luís Guerra e Silva, João Marques-Silva, L. Miguel Silveira, Karem A. Sakallah
Pages: 137-158
DOI: 10.1145/504914.504920
The existence of false paths represents a significant and computationally complex problem in the estimation of the true delay of combinational and sequential circuits. In this article we conduct a comprehensive study of modeling circuit delay...

Constructing and exploiting linear schedules with prescribed parallelism
Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien
Pages: 159-172
DOI: 10.1145/504914.504921
We present two new results of importance in code generation for and synthesis of synchronously scheduled parallel processor arrays and multicluster VLIWs. The first is a new practical method for constructing a linear schedule for the iterations of a...

A fast algorithm for context-aware buffer insertion
Ashok Jagannathan, Sung-Woo Hur, John Lillis
Pages: 173-188
DOI: 10.1145/504914.504922
We study the problem of performing buffer insertion in the context of a given layout. In a practical situation, there are restrictions on where buffers may be inserted; for instance, it may be possible to route wires over a preplaced macro cell, but...

An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications
Ranga Vemuri, Srinivas Katkoori, Meenakshi Kaul, Jay Roy
Pages: 189-216
DOI: 10.1145/504914.504923
We address the problem of register optimization that arises during high-level synthesis from modular hierarchical behavioral specifications. Register optimization is the process of grouping carriers such that each group can be safely allocated to a...

Optimal time borrowing analysis and timing budgeting optimization for latch-based designs
Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
Pages: 217-230
DOI: 10.1145/504914.504924
An interesting property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as long as it can "borrow" time from the shorter paths in the subsequent logic stages. This gives designers a lot of...