Design Automation of Electronic Systems (TODAES)


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ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8 Issue 1, January 2003

Path delay fault testing using test points
S. Tragoudas, N. Denny
Pages: 1-10
DOI: 10.1145/606603.606604
Inserting controllable/observable points in the test architecture has been shown to be a viable method for reducing the number of path delay faults that need to be tested in a circuit. In order to have a minimal impact on the operation clock and more...

Analysis of FPGA/FPIC switch modules
Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
Pages: 11-37
DOI: 10.1145/606603.606605
Switch modules are the most important component of the routing resources in FPGAs/FPICs. Previous works have shown that switch modules with higher routability result in better area performance for practical applications. We consider in this paper an...

Design theory and implementation for low-power segmented bus systems
W.-B. Jone, J. S. Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
Pages: 38-54
DOI: 10.1145/606603.606606
The concept of bus segmentation has been proposed to minimize power consumption by reducing the switched capacitance on each bus [Chen et al. 1999]. This paper details the design theory and implementation issues of segmented bus systems. Based on a...

Floorplan representations: Complexity and connections
Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald Graham
Pages: 55-80
DOI: 10.1145/606603.606607
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this paper, we first present a twin binary trees structure for mosaic floorplans. It is a nonredundant representation. We then derive the exact number of...

Transistor placement for noncomplementary digital VLSI cell synthesis
Michael A. Riepe, Karem A. Sakallah
Pages: 81-107
DOI: 10.1145/606603.606608
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic (CVSL), Pass Transistor Logic (PTL), and domino CMOS. Circuits designed in these noncomplementary...

On the properties of the input pattern fault model
R. D. (Shawn) Blanton, John P. Hayes
Pages: 108-124
DOI: 10.1145/606603.606609
A review of traditional IC failure analysis techniques strongly indicates the need for fault models that directly analyze the function of circuit primitives. The input pattern (IP) fault model is a functional fault model that allows for both complete...

Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications
Tanja Van Achteren, Francky Catthoor, Rudy Lauwereins, Geert Deconinck
Pages: 125-139
DOI: 10.1145/606603.606610
Efficient exploitation of temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications. The effective use of an optimized custom memory hierarchy or a...