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An Approximation Algorithm for Threshold Voltage Optimization

We present a primal-dual approximation algorithm for minimizing the leakage power of an integrated circuit by assigning gate threshold voltages. While... (more)

CASCA: A Design Automation Approach for Designing Hardware Countermeasures Against Side-Channel Attacks

Implementing a cryptographic circuit poses challenges not always acknowledged in the backing mathematical theory. One of them is the vulnerability against side-channel attacks. A side-channel attack is a procedure that uses information leaked by the circuit through, for example, its own power consumption or electromagnetic emissions, to derive... (more)

Detection Mechanisms for Unauthorized Wireless Transmissions

With increasing diversity of supply chains from design to delivery, there is an increasing risk that unauthorized changes can be made within an IC.... (more)

PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer... (more)

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

Field Programmable Gate Array (FPGA) technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long... (more)

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

We present a unified test technique that targets faults in links, routers, and cores of a network-on-chip design based on test sessions. We call an... (more)

UCR: An Unclonable Environmentally Sensitive Chipless RFID Tag For Protecting Supply Chain

Chipless Radio Frequency Identification (RFID) tags that do not include an integrated circuit (IC) in the transponder are more appropriate for supply-chain management of low-cost commodities and have been gaining extensive attention due to their relatively lower price. However, existing chipless RFID tags consume considerable tag area and... (more)

SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs

In this article, we present SHAIP, a secure Hamming distance–based mutual authentication protocol. It allows an unlimited number of authentications by employing an intrinsic Physical Unclonable Function (PUF). PUFs are being increasingly employed for remote authentication of devices. Most of these devices have limited resources. Therefore,... (more)

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

This article presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design... (more)

Learning From Sleeping Experts: Rewarding Informative, Available, and Accurate Experts

We consider a generalized model of learning from expert advice in which experts could abstain from participating at some rounds. Our proposed online algorithm falls into the class of weighted average predictors and uses a time-varying multiplicative weight update rule. This update rule changes the weight of an expert based on his or her relative... (more)

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ACM TODAES new page limit policy: Manuscripts must be formatted in the ACM Transactions format; a 35-page limit applies to the final paper. Rare exceptions are possible if recommended by the reviewers and approved by the Editorial Board.

ORCID is a community-based effort to create a global registry of unique researcher identifiers for the purpose of ensuring proper attribution of works to their creators. When you submit a manuscript for review, you will be presented with the opportunity to register for your ORCID.

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Forthcoming Articles
Reconfigurable Battery Systems: A Survey on Hardware Architecture and Research Challenges

In a reconfigurable battery pack, the connections among cells can be changed during operation, to form different configurations. This can lead a battery, a passive two-terminal device, to a smart battery which can reconfigure itself according to the requirement to enhance operational performance. Several hardware architectures with different levels of complexities have been proposed. Some researchers have used existing hardware and demonstrated improved performance on the basis of novel optimization and scheduling algorithms. The possibility of software techniques to benefit the energy-storage systems is exciting and it is the perfect time for such methods as the need of high performance and long lasting batteries is on the rise. This novel field requires new understanding, principles and evaluation metrics of proposed schemes. In this paper, we systematically discuss and critically review state-of-art. This is the first effort to compare the existing hardware topologies in terms of flexibility and functionality. We provide a comprehensive review that encompasses all existing research works starting from the details of the individual battery including modeling and properties as well as fixed-topology traditional battery packs. To stimulate further research in this area, we highlight key challenges and open problems in this domain.

Compilation of Dataflow Applications for Multi-cores using Adaptive Multi-objective Optimization

State-of-the-art system synthesis techniques employ meta-heuristic optimization techniques for DSE to tailor application execution, e.g. defined by a dataflow graph, for a given target platform. Unfortunately, performance evaluation of implementations is computationally very expensive as this involves compilation to and extensive evaluation on the target hardware. Applying heuristics for performance evaluation allows for a reduction of the exploration time but may deteriorate the convergence of the optimization technique towards performance-optimal solutions. Hence, we propose DSE strategies that are able to dynamically trade off between (a) approximating heuristics to guide the exploration and (b) accurate measurement-based performance evaluation. This is achieved by introducing a set of additional, but easily computable guiding objective functions, and varying the set of objective functions that are evaluated during the DSE adaptively. These guiding objectives are generically applicable for dataflow models without having to apply any configuration techniques to tailor their parameters to the specific use case. Results for synthetic benchmarks as well as a real-world application demonstrate that our approaches clearly outperform a state-of-the-art approach from literature in terms of implementation quality as well as exploration times. We show a 2-core implementation where after 3 hours of exploration time one of our proposed adaptive DSE strategies already obtains a 60% higher throughput than obtained by the state-of-the-art approach. Even when the state-of-the-art approach is given a exploration time of more than 2 weeks to optimize this value, the proposed adaptive DSE strategy features a 20% higher throughput after a exploration time of about 4 days.

Data-driven Anomaly Detection with Timing Features for Embedded Systems

Malware is a serious threat to network-connected embedded systems, as evidenced by the continued and rapid growth of such devices, commonly referred to as of the Internet of Things. Their ubiquitous use in critical applications require robust protection to ensure user safety and privacy. That protection must be applied to all system aspects, extending beyond protecting the network and external interfaces. Anomaly detection is one of the last lines of defence against malware, in which data-driven approaches that require the least domain knowledge are popular. However, embedded systems, particularly edge devices, face several challenges in applying data-driven anomaly detection, including unpredictability of malware, limited tolerance to long data collection windows, and limited computing/energy resources. In this paper, we utilize subcomponent timing information of software execution, including intrinsic software execution, instruction cache misses, and data cache misses as features, to detect anomalies based on ranges, multidimensional Euclidean distance, and classification at runtime. Detection methods based on lumped timing range are also evaluated and compared. We design several hardware detectors implementing these data-driven detection methods, which non-intrusively measuring lumped/subcomponent timing of all system/function calls of the embedded application. We evaluate the area, power, and detection latency of the presented detector designs. Experimental results demonstrate that the subcomponent timing model provides sufficient features to achieve high detection accuracy with low false positive rates using a one-class support vector machine, considering sophisticated mimicry malware.

A Cross-Level Verification Methodology for Digital IPs Augmented with Embedded Timing Monitors

A Novel Resistive Memory based Process-In-Memory Architecture for Efficient Logic and Add Operations

The coming era of big data revives the Processing-In-Memory (PIM) architecture to relieve the memory wall problem that embarrasses the modern computing system. However, most existing PIM designs just put computing units closer to memory, rather than a complete integration of them due to their incompatibility in CMOS manufacturing. Fortunately, the emerging Resistive-RAM (ReRAM) offers new hope to this dilemma owing to its inherent memory and computing capability using the same device. In this paper, we propose a ReRAM memory structure with efficient PIM capability of both logic and add operations. It first leverages non-linearity to suppress \emph{sneak current} and thus sustains high memory density. Using a differential bit cell, it also enables efficient processing of arbitrary logic functions using the same memory cells with non-destructive operations. Then, a novel PIM adder is proposed, which customizes a sneak current path as the carry-chain for fast carry propagation and improves adder performance significantly. In the experiment, the proposed PIM demonstrates higher efficiency in both computing area and performance for logic and addition, which greatly increases the ReRAM PIM applicability for future computable architectures.

Thermal-aware 3D Symmetrical Buffered Clock Tree Synthesis

The semiconductor industry has accepted three dimensional integrated circuits (3D ICs) as a possible solution to address speed and power management problems. In addition, 3D ICs have recently demonstrated a huge potential in reducing wire length and increasing the density of a chip. However, the growing density in chips such as TSV-based 3D ICs has brought the increased temperature on chip and temperature gradients depending on location. Thus, through silicon via (TSV)-based 3D clock tree synthesis (CTS) causes thermal problem leading to large clock skew. We propose a novel 3D symmetrical buffered clock tree synthesis considering thermal variation. First, 3D abstract tree topology based on nearest neighbor selection with median cost (3D-NNM) is constructed by pairing sinks that have similar power consumption. Second, the layer assignment of internal nodes is determined for uniform TSV distribution. Third, in thermal-aware 3D deferred merging embedding (DME), the exact location of TSV is determined and wire routing/buffer insertion are performed after the thermal profile based on grid is obtained. The proposed method is verified using a 45nm process technology and utilized a predictive technology model (PTM) with HSPICE. Also, is evaluated for the IBM benchmarks and ISPD09 benchmarks with no blockages. In experimental result, we can achieve average 18% of clock skew reduction compared to existing thermal-aware 3D CTS. Therefore, thermal-aware 3D symmetrical buffered clock tree synthesis presented in this work is very efficient for circuit reliability.

Design Automation for Dilution of a Fluid using Programmable Microfluidic Device based Biochips

Microfluidic lab-on-a-chips has emerged as a new technology for implementing biochemical protocols on small-sized portable devices targeting low-cost medical diagnostics. Among various efforts of fabrication of such chips, a relatively new technology is programmable microfluidic device (PMD) for implementation of flow-based lab-on-a-chips. A PMD chip is suitable for automation due to its symmetric nature. In order to implement a bioprotocol on such a reconfigurable device, it is crucial to automate sample preparation on-chip as well. In this paper, we propose a dilution algorithm (namely DPMD) and its architectural mapping scheme (namely GAMA) for addressing fluidic cells of such a device to perform dilution of a reagent fluid on-chip. We used an optimization function that first minimizes the number of mixing steps and then reduces the waste generation and further reagent requirement. Simulation results show that the proposed DPMD scheme is comparative to existing state-of-the-art dilution algorithm. The proposed design automation using architectural mapping scheme reduces the required chip area, hence, minimizes the valve switching that, in turn, increases the life-span of PMD-chip.

SSA-AC: Static Significance Analysis for Approximate Computing

Recently, the quest to reduce energy consumption in digital systems has been the subject of a number of ongoing studies. One of the most researched focuses is ?Approximate Computing (AC).? AC is a new computing paradigm in both hardware and software designs that aim to achieve energy-efficient digital systems. Although a variety of AC techniques have been studied so far, the main question ?how (in which section) can a program or a circuit be approximated?? has not been answered yet. This work addresses the above issue by developing a software framework SSA-AC (Static Significance Analysis for Approximate Computing) to analyze the target application program and guide the designers to identify parts of the program to which approximation can or cannot be applied. SSA-AC statically analyzes the significance of variables in the precise version of the program and thus needs no trial-and-error evaluation or specific test data. Experimental results show that SSA-AC can successfully extract the significance ranking of inputs/variables to be approximated in a much shorter time than existing statistical works that are inevitably data-dependent.

Adaptive Test for RF/Analog Circuit Using Higher Order Correlations Among Measurements

As process variations increase and devices get more diverse in their behavior, using the same test list for all devices is increasingly inefficient. Methodologies that adapt the test sequence with respect to lot, wafer, or even device?s own behavior help contain the test cost while maintaining test quality. In adaptive test selection approaches, initial test list, a set of tests that are applied to all devices to learn information, plays a crucial role in the quality outcome. Most adaptive test approaches select this initial list based on fail probability of each test individually. Such a selection approach does not take into account the correlations that exist among various measurements and potentially will lead to the selection of correlated tests. In this work, we propose a new adaptive test algorithm that includes a mathematical model for initial test ordering that takes correlations among measurements into account. The proposed method can be integrated within an existing test flow running in the background to improve not only the test quality but also the test time. Experimental results using four distinct industry circuits and large amounts of measurement data show that the proposed technique outperforms prior approaches considerably.

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