ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and cannot be adjusted to different applications. Furthermore, clock routing resources are typically... (more)

Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints

The legalization step is performed after global placement where wire length and routability are optimized or during timing optimization where buffer insertion or gate sizing are applied to meet timing requirements. Therefore, an ideal legalization approach must preserve the quality of the input placement in terms of routability, wire length, and... (more)

Variation-Aware Global Placement for Improving Timing-Yield of Carbon-Nanotube Field Effect Transistor Circuit

As the conventional silicon-based CMOS technology marches toward the sub-10nm region, the problem of... (more)

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction

Owing to existing intellectual properties, prerouted nets, and power/ground wires, the routing of a system on chip design demands to detour around multilayer obstacles. Traditional approaches... (more)

Ordered Escape Routing with Consideration of Differential Pair and Blockage

Ordered escape routing is a critical issue in high-speed PCB routing. Differential pair and thermal-blockage-avoided are useful in PCB design to... (more)

Routable and Matched Layout Styles for Analog Module Generation

Two1 novel automatic generation methods for analog layout—a symmetrical twin-row method for MOS transistors and a twisted common-centroid... (more)

iTimerM: A Compact and Accurate Timing Macro Model for Efficient Hierarchical Timing Analysis

As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this article, we present compact and accurate timing macro modeling, which is the key to efficient and accurate hierarchical timing analysis. Our goal is to contain only a minimal amount of interface logic in our timing macro model.... (more)

Optimal Allocation of LDOs and Decoupling Capacitors within a Distributed On-Chip Power Grid

Parallel on-chip voltage regulation, where multiple regulators are connected to the same power grid, has recently attracted significant attention with... (more)

Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs

Outsourcing of design and manufacturing processes makes integrated circuits (ICs) vulnerable to adversarial changes and raises concerns about their... (more)


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Forthcoming Articles
An approximation algorithm for threshold voltage optimization

We present a primal-dual approximation algorithm for minimizing the leakage power of an integrated circuit by assigning gate threshold voltages. While most existing techniques do not provide a performance guarantee, we prove an upper bound on the power consumption. The algorithm is practical and works with an industrial sign-off timer. It can be used for post-routing power reduction or for optimizing leakage power throughout the design flow. We demonstrate the practical performance on recent microprocessor units. Our implementation obtains significant leakage power reductions of up to 8% on top of one of the most successful algorithms for gate sizing and threshold voltage optimization. After timing-aware global routing we achieve leakage power reductions of up to 34%.

Toward Effective Reliability Requirement Assurance for Automotive Functional Safety

Reliability is an important automotive functional safety property, and the reliability requirement of safety-critical automotive function must be assured. Pre-assigning reliability values to unassigned tasks by transferring the reliability requirement of the function to each task is a useful reliability requirement assurance approach proposed in recent years. However, the pre-assigned reliability values in state-of-the-art studies are pessimistic toward ineffective reliability requirement assurance, thereby resulting in a limited reduction in response time. This study presents the geometric mean-based non-fault-tolerant reliability pre-assignment (GMNRP) and geometric mean-based fault-tolerant reliability pre-assignment (GMFRP) approaches, in which geometric mean-based reliability values are pre-assigned to unassigned tasks. Geometric mean can make the pre-assigned reliability values of unassigned tasks to the central tendency. Experimental results show that GMNRP and GMFRP can effectively reduce the response time compared with their individual state-of-the-art counterparts.

CASCA: a Design Automation Approach for Designing Hardware Countermeasures Against Side Channel Attacks

Implementing a cryptographic circuit poses challenges not always acknowledged in the backing mathematical theory. One of them is the vulnerability against \emph{side channel attacks}. A side channel attack is a procedure that uses information leaked by the circuit through, for example, its own power consumption or electromagnetic emissions, to derive sensitive data (e.g, the secret key used for encryption). Nowadays, we design circuitry to keep this sensitive information from leaking (i.e., a \emph{countermeasure}), but the path from specification down to implementation is far from being fully automatic. As we know, manual refinement steps can be error prone and the sheer potential of these errors can be devastating in a scenario such as the one we are dealing with. In this paper, we investigate whether a single embedded domain specific language (EDSL) can, at the same time, help us specifying and enforcing the functionality of the circuit as well as its protection against side-channel attacks. The EDSL is a fundamental block of an original design flow (named Countermeasure Against Side-Channel Attacks, i.e., CASCA) whose aim is to complement an existing industrial scenario and to provide the necessary guarantee that a secure primitive is not vulnerable up to a first order attack. As a practical case study, we will show how we applied the proposed tools to ensure both functional and extra-functional correctness of a composite-field AES S-Box.

Performance and Thermal Trade-Offs for Energy Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy efficient network on chip (NoC) architectures as communication backbones for manycore chips. To exploit the benefits of the vertical dimension of 3D integration, through-silicon-via (TSV) has been predominantly used in state-of-the-art manycore chip design. However, for TSV-based systems, high power density and the resultant thermal hotspot remain major concerns from the perspectives of chip functionality and overall reliability. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage-Frequency-Island (VFI)-based power management strategy. However, due to inherent thermal constraints of a TSV-based 3D system, we are unable to fully exploit the benefits offered by the power management methodology. In this context, emergence of monolithic 3D (M3D) integration has opened up new possibility of designing ultra-low-power and high-performance circuits and systems. The smaller dimensions of the inter-layer dielectric (ILD) and monolithic inter-tier vias (MIVs) offer high-density integration, flexibility of partitioning logic blocks across multiple tiers, and significant reduction of total wire-length. In this work, we present the first-ever study of the performance-thermal trade-offs for energy efficient monolithic 3D manycore chips. In particular, we present a comparative performance evaluation of M3D NoCs with respect to their conventional TSV-based counterparts. We demonstrate that the proposed M3D-based NoC architecture incorporating VFI-based power management achieves a maximum of 29.4% lower energy-delay-product (EDP) compared to the TSV-based designs for a large set of benchmarks. We also demonstrate that the M3D-based NoC shows up to 29.1% lower maximum temperature than the TSV-based counterpart for these benchmarks.

Dynamically-Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences

Earlier works observed that certain primary inputs have preferred values, which help increase the gate-level fault coverage when they appear in a functional test sequence. This paper observes that multiplexers present additional opportunities for increasing the fault coverage of a functional test sequence, which are not captured by preferred primary input values. Because multiplexers are prevalent, their effect on the fault coverage can be significant. A static analysis, that is independent of any functional test sequence, is performed in this paper to identify preferred values for the outputs of multiplexers. This is followed by a dynamic analysis that adjusts the select inputs of the multiplexers for a given functional test sequence in order to ensure that the preferred values appear on the outputs of the multiplexers more often. The analysis yields design-for-testability logic for the select inputs of the multiplexers that have preferred values. The logic is independent of the functional test sequence, and it allows the fault coverage to be increased when the select inputs are not primary inputs, or when the same select inputs are used for different multiplexers. Experimental results are presented to demonstrate that this approach has a significant effect on the fault coverage of functional test sequences.

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

This paper presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). STT-based LUT with significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study conducted on a large number of standard circuit benchmarks concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact on the performance of the circuit. We also tested these techniques against satisfiability attacks developed recently and show that these techniques also render more advanced reverse-engineering techniques computationally infeasible.

Optimal Allocation of Computation and Communication in an IoT Network

Internet of things (IoT) is being developed for a wide range of applications from home automation and personal fitness, to smart cities. With the extensive growth in adaptation of IoT devices, comes the uncoordinated and substandard designs aimed at promptly making products available to the end consumer. This substandard approach restricts the growth of IoT in the near future and necessitates studies to understand requirements for an efficient design. A particular area where IoT applications have grown significantly is the surveillance and monitoring. Applications of IoT in this domain are relying on distributed sensors, each equipped with a battery, capable of collecting images, processing images, and communicating the raw or processed data to the nearest node until it reaches the base station for decision making. In such an IoT network where processing can be distributed over the network, the important research question is how much of data each node should process and how much it should communicate for a given objective. This work answers this question and provides a deeper understanding of energy and delay trade-offs in an IoT network with three different target metrics.

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

We present a unied test technique that targets faults in links, routers, and cores of a network-on- chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test packets for routers are delivered to them via the fault- free links and routers that were identied in the previous test sessions to avoid packet corruption. Test packet delivery for routers is implemented as a fault-tolerant unicast-based multicast scheme within the tested part of the network-on-chip. A new fault-tolerant routing algorithm is proposed for unicast-based multicast test delivery. Identical cores share the same test set, and they are tested within the same test session. Simulation results highlight the eectiveness of the proposed method in reducing test time.

Quality-Enhanced OLED Power Savings on Mobile Devices

In the future, mobile systems will increasingly feature more advanced organic light-emitting diode (OLED) displays. The power consumption of these displays is highly dependent on the image content. However, existing OLED power-saving techniques either change the visual experience of users or degrade the visual quality of images in exchange for a reduction in the power consumption. Some techniques attempt to enhance the image quality by employing a compound objective function. In this paper, we present a win-win scheme that always enhances the image quality while simultaneously reducing the power consumption.We define metrics to assess the benefits and cost for potential image enhancement and power reduction. We then introduce algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Next, the win-win scheme is extended to process videos at a justifiable computational cost. All the proposed algorithms are shown to possess the win-win property without assuming accurate OLED power models. Finally, the proposed scheme is realized through a practical camera application and a video camcorder on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database and a smartphone with real-world videos are very encouraging and provide valuable insights for future research and practices.

Rapid Triggering Capability using an Adaptive Overlay during FPGA Debug

FPGA technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long design and debug cycles. To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required upon modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for trigger-type circuits. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40 seconds instead of recompiling the circuit during debug iterations, increasing debug productivity.

Guiding Formal Verification Orchestration Using Machine Learning Methods

Typical modern HW designs include many blocks associated with thousands of design properties. Having todays commercial formal verifiers utilize a complementary set of state-of-art formal algorithms is a key in enabling the formal verification tools to successfully cope with verification problems of different sizes, types and complexities. Formal engines orchestration is the methodology used to pick up the most appropriate formal engine for a specific verification problem. It assures proper scheduling of the formal engines to minimize the time consumed to solve individual design verification problems, hence highly impacts the time required to verify the overall design properties. This work proposes the utilization of supervised machine learning classification techniques to guide the orchestration step by predicting the formal engines that should be assigned to design property. Up to 16,500 formal verification runs on RTL designs and their properties are used to train the classifier to create a prediction model. The classifier assigns any new verification problem to an appropriate list of formal engines associated with a probability distribution over the set of engines classes. Our results indicate how the proposed model is able to improve the formal suite total run time by up to 98% of its maximum allowable time improvement using multi-classification based orchestration and to nominate with 88% accuracy the appropriate formal engines for new-to-verify HW designs.

GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

Optimizing for routability during FPGA placement is becoming increasingly important, as failure to spread congestion throughout the chip, especially in the case of large designs, may result in placements that either cannot be routed, or that require the router to work excessively hard to obtain success. In this paper, we introduce a new, analytic routability-aware placement algorithm for Xilinx UltraScale FPGA architectures. The proposed algorithm, called GPlace3.0, seeks to optimize both wirelength and routability. Our work contains several unique features including a novel window-based procedure for satisfying legality constraints in lieu of packing, an accurate congestion estimation method based on modifications to the pathfinder global router, and a novel detailed placement algorithm that optimizes both wirelength and external pin count. Experimental results show that compared to the top three winners at the recent ISPD'16 FPGA placement contest, GPlace3.0 is able to achieve (on average) a 7.53%, 15.15%, and 33.50% reduction in routed wirelength, respectively, while requiring less overall runtime. As well, an additional 360 benchmarks were provided directly from Xilinx Inc. These benchmarks were used to compare GPlace3.0 to the most recently improved versions of the first and second place contest winners. Subsequent experimental results show that GPlace3.0 is able to outperform the improved placers in a variety of areas including number of best solutions found, fewest number of benchmarks that cannot be routed, runtime required to perform placement, and runtime required to perform routing.

PV -Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this paper, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the operational efficiency. Our experimental results show that the proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.

P3: Privacy Preserving Positioning for Smart Automotive Systems

This paper presents the first provably secure localization method for smart automotive systems. Using this method, a car, lost due to unavailability of GPS, can compute its location with assistance from three nearby cars while the locations of all the participating cars including the lost car remain private. Technological enhancement of modern vehicles, especially in navigation and communication, necessitates parallel enhancement in security and privacy. Previous approaches to maintaining user location privacy suffered from one or more of the following drawbacks: trade-off between accuracy and privacy, one-sided privacy and need of a trusted third party that presents a single point to attack. The localization method presented here is one of the very first location-based services that eliminates all these drawbacks. Two protocols for computing the location is presented here based on two Secure Function Evaluation (SFE) techniques that allow multiple parties to jointly evaluate a function on inputs which are encrypted to maintain privacy. The first one is based on the two-party protocol named Yaos Garbled Circuit (GC). The three assisting cars participate in a total six invocations of the two-party GC operation to compute the location of the lost car without revealing their location to one another. The second one is based on only one invocation of the Beaver-Micali-Rogaway (BMR) protocol that allows inputs from more than two parties. The two secure localization protocols exhibit trade-offs between performance and resilience against collusion. Along with devising the protocols we design and optimize netlists for the functions required for computation of location by leveraging conventional logic synthesis tools with custom libraries optimized for SFE. Proof-of-concept implementation of the protocol shows that the complete operation can be performed within only 355 ms. The fast computing time enables localization of even moving cars.

Trading-Off Power Consumption and Prediction Performance in Wearable Motion Sensors: An Optimal and Real-Time Approach

Power consumption is identified as one of the main complications in designing practical wearable systems, mainly due to their stringent resource limitations. When designing wearable technologies, several system-level design choices, which directly contribute to the energy consumption of these systems, must be considered. In this paper, we propose a lightweight system optimization framework that trades-off power consumption and performance in connected wearable motion sensors. While existing approaches, exclusively focus on one or few specific design variables, our framework holistically finds the optimal power-performance solution with respect to the specified application need. This is formulated as a multi-variant non-convex optimization problem and therefore is hard to solve. To decrease the complexity, we propose a smoothing function to reduce this optimization to a convex problem. The reduced optimization is then solved in linear time using a devised derivative-free optimization approach, namely cyclic coordinate search. We evaluate our framework against several holistic optimization baselines using a real-world wearable activity recognition dataset. We minimize the energy consumption for various activity recognition performance thresholds ranging from 40% to 80% and demonstrate up to 64% energy saving.

Knowledge and Simulation Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications

We propose a passive, fully-differential, synthesizable zoom-ADC architecture for BIST applications, along with a synthesis tool that can target various design specifications. We present the detailed ADC architecture and a step by step process designing the zoom-ADC. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 91dB SNR in 512¼s measurement time and consumes 14.95¼W power. The second design achieves 78.2dB SNR in 31.25¼s measurement time and consumes 60¼W power.

Non-Intrusive In-Situ Requirements Monitoring of Embedded System

Accounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. Monitoring and verifying system requirements at runtime enables a system to continuously and introspectively ensure the system is operating correctly in the presence of dynamic execution scenarios. In this paper, we present a requirements-driven methodology enabling efficient runtime monitoring of embedded systems. The proposed approach extracts a runtime monitoring graph from system requirements specified using UML sequence diagrams. Non-intrusive, on-chip hardware dynamically monitors the system execution, verifies the execution adheres to the requirements model, and in the event of a failure provides detailed information that can be analyzed to determine the root cause. Using case studies of an autonomous vehicle and pacemaker prototypes, we analyze the relationship between event coverage, detection rate, and hardware requirements.

Distributed Machine Learning on Smart-gateway Network towards Real-time Smart-grid Energy Management with Behavior Cognition

Real-time data analytics for smart-grid energy management is challenging with consideration of both occupant behavior profiles and energy profiles. This paper proposes a distributed and networked machine learning platform on smart-gateway based smart-grid. It can analyze occupant behaviors, provide short-term load forecasting and allocate renewable energy resources. Firstly, occupant behavior profile is captured by real-time indoor positioning system with WiFi data analytics; and the energy profile is extracted by real-time meter system with electricity load data analytics. Then, the 24-hour occupant behavior profile and energy profile are fused with prediction using an online distributed machine learning algorithm with real-time data update. Based on the forecasted occupant behavior profile and energy profile, solar energy source is allocated to reduce peak demand on the main electricity power-grid. The whole management flow can be operated on the distributed smart-gateway network with limited computational resources but with a supported general machine-learning engine. Experimental results on occupant behavior extraction show that the proposed algorithm can achieve 50 times and 38 times speed-up during data testing and training respectively with comparable indoor positioning accuracy, when compared to traditional support vector machine (SVM) method. Furthermore, for short-term load forecasting, it is 14.83% more accurate when compared to SVM based data analytics. Based on the predicted occupant behavior profile and energy profile, our proposed energy management system (EMS) can achieve 19.66% more peak load reduction and 26.41% more cost saving as compared to the SVM based method.

Instinctive Assistive Indoor Navigation using Distributed Intelligence

The development of cyber-physical systems and the Internet of Things (IoT) have a signifcant potential to improve the eectiveness of assistive technologies for those with physical disabilities. To be practical, assistive systems should minimize the number of inputs from users, reducing cognitive and physical eort required. This paper presents a versatile, energy-efcient framework and algorithm for assistive indoor navigation using an electric wheelchair and user inputs from multiple modalities. The proposed algorithm automates indoor navigation using only a few user commands captured through a wearable device, with the goal of simplifying navigation tasks and making them more instinctive for the user. We evaluated the proposed methodology using both a virtual smart building and a prototype built with o-the-shelf IoT development boards. Our evaluations for three dierent oorplans show one order of magnitude reduction in user eort and communication energy required for navigation when compared with conventional navigation methodologies that require continuous user inputs.

Switching Predictive Control Using Reconfigurable State-Based Model

Advanced control methodologies have helped the development of modern vehicles that are capable of path planning and path following. For instance, Model Predictive Control (MPC) employs a predictive model to predict the behavior of the physical system for a specific time horizon in the future. An optimization problem is solved to compute optimal control actions while handling model uncertainties and nonlinearities. However, these prediction routines are computationally intensive and the computational overhead grows with the complexity of the model. \textit{Switching MPC} addresses this issue by combining multiple predictive models, each with a different precision granularity. In this paper, we proposed a novel switching predictive control method based on a model reduction scheme to achieve various model granularities for path following in autonomous vehicles. A state-based model with tunable parameters is proposed to operate as a reconfigurable predictive model of the vehicle. A run-time switching algorithm is presented that selects the best model using machine learning. We employed a metric that formulates the trade-off between the error and computational savings due to model reduction. Our simulation results show that the use of the predictive model in the switching scheme as opposed to single granularity scheme yields a 45% decrease in execution time in trade-off for a small 12% loss in accuracy in prediction of future outputs and no loss of accuracy in tracking the reference trajectory.

UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag For Protecting Supply Chain

Chipless Radio Frequency Identification (RFID) tags that do not include an integrated circuit (IC) in the transponder are more appropriate for supply chain management of low-cost commodities and have been gaining extensive attention due to their relatively lower price. However, existing chipless RFID tags consume considerable tag area and manufacturing time/cost because of complex fabrication process (e.g., requiring removing or shorting some resonators on the tag substrate to encode data). Worse still, their identifiers (IDs) are deterministic, clonable, and small in terms of bitwidth. To address these shortcomings and help preserve the cold chain for commodities (e.g., vaccines, pharmaceuticals, etc.) sensitive to temperature, we develop a novel unclonable environmentally-sensitive chipless RFID (UCR) tag that intrinsically generates a unique ID from both manufacturing variations and ambient temperature variation. UCR tag consists of two parts: (i) a certain number of concentric ring slot resonators integrated on a certain laminate (e.g., TACONIC TLX-0), whose resonance frequencies rely on slot geometric parameters and substrate dielectric constant that are sensitive to manufacturing variations; and (ii) a standalone circular ring slot resonator integrated on a particular substrate (e.g., grease) that will be melted at a high temperature, whose resonance frequency relies on geometric parameters of slot resonator, substrate dielectric constant, and ambient temperature. UCR tags have the capability to track commodities and their temperatures in the supply chain. The area of UCR tag is comparable to regular quick response (QR) code. Experimental results based on UCR tag prototypes have verified their uniqueness and reliability.

Enhancing Flash Memory Reliability by Jointly Considering Write-back Pattern and Block Endurance

Owing to high cell density caused by the advanced manufacturing process, the reliability of flash drives turns out to be rather challenging in flash system designs. In order to enhance the reliability of flash drives, error-correcting code (ECC) has been widely utilized in flash drives to correct error bits during programming/reading data to/from flash drives. Although ECC can effectively enhance the reliability of flash drives by correcting error bits, the capability of ECC would degrade while the program/erase (P/E) cycles of flash blocks is increased. Finally, ECC could not correct a flash page because a flash page contains too many error bits. As a result, reducing error bits is an effective solution to further improve the reliability of flash drives when a specific ECC is adopted in the flash drive. This work focuses on how to reduce the probability of producing error bits in a flash page. Thus, we propose a pattern-aware write strategy for flash reliability enhancement. The proposed write strategy considers both the P/E cycle of blocks and the pattern of written data while a flash block is allocated to store the written data. Since the proposed write strategy allocates young blocks (resp. old blocks) for hot data (resp. cold data) and flips the bit pattern of the written data to the appropriate bit pattern, the proposed strategy can effectively improve the reliability of flash drives. The experimental results show that the proposed strategy can reduce the number of error pages by up to 50\%, compared with the well-known DFTL solution. Moreover, the proposed strategy is orthogonal with all ECC mechanisms so that the reliability of the flash drives with ECC mechanisms can be further improved by the proposed strategy.

SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties

Temperature is a critical property of smart systems, due to its impact on reliability and to its inter-dependence with power consumption. Unfortunately, the current design flows evaluate thermal evolution ex-post, on offline power traces. This does not allow to consider temperature as a dimension in the design loop, and it misses all the complex inter-dependencies with design choices and power evolution. In this paper, by adopting the functional language SystemC-AMS, we propose a method to enable thermal/power/functional co-simulation. The system thermal model is built by using state-of-the-art circuit equivalent models, by exploiting the support for electrical linear networks intrinsic of SystemC-AMS. The experimental results will show that the choice of SystemC-AMS is a winning strategy for building a simultaneous simulation of multiple functional and extra-functional properties of a system. The generated code exposes an accuracy comparable to that of reference thermal simulator HotSpot. Additionally, the initial overhead due to the general purpose nature of SystemC-AMS is compensated by surprisingly high performance of transient simulation, with speedups as high as two orders of magnitude. The application of the proposed methodology to a set of benchmarks, used for the IEEE PATMOS design contest, will additionally prove the effectiveness of the SystemC-AMS thermal simulator.

Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops

The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show how to modify the Boolean network describing a combinational logic to increase the opportunities for folding, without affecting its function. Experiments with benchmark circuits achieved an average reduction in circuit area of 18%.

A Comprehensive Side Channel Information Leakage Analysis of an In-order RISC CPU Microarchitecture

Side channel attacks are a prominent threat to the security of embedded systems. To lead one, an adversary evaluates the goodness of fit of a key dependent model to the side channel measurements taken from an actual device, identifying the secret key value as the one yielding the best fitting model. We investigate the mapping between the models and the sources of information leakage in the CPU microarchitecture in a post map simulation environment and classify the leakage sources affecting different parts of the microarchitecture, Finally, we provide are able to provide hints to the software architect on potential vulnerabilities.

An Algorithmic Approach to Formally Verify an ECC Library

The weakest link in Cryptosystems is quite often due to the implementation rather than the mathematical underpinnings. A vast majority of attacks in the recent past have targeted programming flaws and bugs to break security systems. Due to the complexity, empirically verifying such systems is practically impossible, while manual verification as well as testing do not provide adequate guarantees. In this paper, we leverage model checking techniques to prove the functional correctness of an Elliptic curve cryptography (ECC) library with respect to its formal specification. We demonstrate how the huge state space of the C library can be aptly verified using a hierarchical assume-guarantee verification strategy. To test the scalability of this approach, we verify the correctness of four NIST-specified elliptic curve implementations. The smallest curve with a 192 bit prime field took 1 day to verify, while the largest curve with a 384 bit prime field took 8 days to verify.

Detection Mechanisms for Unauthorized Wireless Transmissions

With increasing diversity of supply chains from design to delivery, there is an increasing risk that unauthorized changes can be made within an IC. One of the motivations for this type of change is to learn important information (such as encryption keys, spreading codes) from the hardware, and transmit this information to a malicious party. To evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present several signal processing techniques to detect unauthorized transmissions which can be hidden within the legitimate signal. We employ a scheme where the legitimate transmission is configured to emit a single sinusoidal waveform. We use time and spectral domain analysis techniques to explore the transmit spectrum. Since every transmission, no matter how low the signal power is, must have a spectral signature, we identify unauthorized transmission by eliminating the desired signal from the spectrum after capture. Experiment results how that when spread spectrum techniques are used, the presence of an unauthorized signal can be determined without the need for decoding the malicious signal. The proposed detection techniques need to be used as enhancements to the regular testing and verification procedures if hardware security is a concern.

Learning From Sleeping Experts: Rewarding Informative, Available, and Accurate Experts

We consider a generalized model of learning from expert advice in which experts could abstain from participating at some rounds. Our proposed online algorithm falls into the class of weighted average predictors and uses a time varying multiplicative weight update rule. This update rule changes the weight of an expert based on his relative performance compared to the average performance of available experts at the current round. This makes the algorithm suitable for recommendation systems in the presence of an adversary with many potential applications in the new emerging area of Internet of Things. We prove the convergence of our algorithm to the best expert, defined in terms of both availability and accuracy, in the stochastic setting. In particular, we show the applicability of our definition of best expert through convergence analysis of another well-known algorithm in this setting. Finally, through simulation results on synthetic and real datasets we justify the out-performance of our proposed algorithms compared to the existing ones in the literature.


Publication Years 1996-2018
Publication Count 991
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First Name Last Name Award
Mohammad Abdullah Al Faruque ACM Senior Member (2017)
Iris Bahar ACM Distinguished Member (2012)
Luca Benini ACM Fellows (2016)
Robert Brayton ACM Paris Kanellakis Theory and Practice Award (2006)
Krishnendu Chakrabarty ACM Fellows (2013)
ACM Distinguished Member (2008)
ACM Senior Member (2006)
Naehyuck Chang ACM Fellows (2015)
ACM Distinguished Member (2012)
ACM Senior Member (2007)
Danny Z Chen ACM Distinguished Member (2014)
ACM Senior Member (2011)
Jason Cong ACM Fellows (2008)
Giovanni DeMicheli ACM Fellows (2001)
Srinivas Devadas ACM Fellows (2014)
Nikil D. Dutt ACM Fellows (2014)
ACM Distinguished Member (2007)
Lieven Eeckhout ACM Senior Member (2016)
Suhaib A Fahmy ACM Senior Member (2013)
Franz Franchetti ACM Senior Member (2015)
ACM Gordon Bell Prize (2006)
W. Kent Fuchs ACM Fellows (2000)
Soheil Ghiasi ACM Senior Member (2015)
Ronald L. Graham ACM Fellows (1999)
Aarti Gupta ACM Fellows (2017)
Prosenjit Gupta ACM Senior Member (2008)
Rajesh Gupta ACM Fellows (2016)
Rajiv Gupta ACM Fellows (2009)
Matthew Guthaus ACM Senior Member (2013)
John P Hayes ACM Fellows (2001)
Pao-Ann Hsiung ACM Senior Member (2006)
Mary Jane Irwin ACM Athena Lecturer Award (2010)
ACM Distinguished Service Award (2005)
ACM Fellows (1996)
Andrew Kahng ACM Fellows (2012)
Sung Mo Kang ACM Fellows (2001)
Kenneth W Kennedy ACM Fellows (1995)
Tei-Wei Kuo ACM Fellows (2015)
John Lee ACM Senior Member (2014)
Roman Lysecky ACM Senior Member (2014)
Sharad Malik ACM Fellows (2014)
Diana Marculescu ACM Distinguished Member (2011)
ACM Senior Member (2009)
Igor Markov ACM Distinguished Member (2011)
ACM Senior Member (2007)
Sally A. McKee ACM Senior Member (2013)
Prabhat Mishra ACM Distinguished Member (2015)
ACM Senior Member (2010)
Saraju P. Mohanty ACM Senior Member (2010)
Trevor Mudge ACM Fellows (2016)
ACM-IEEE CS Eckert-Mauchly Award (2014)
Walid Najjar ACM Distinguished Member (2015)
ACM Senior Member (2014)
Steven M Nowick ACM Senior Member (2009)
Krishna Palem ACM Fellows (2005)
Ian Parberry ACM Distinguished Member (2015)
Janak H Patel ACM Fellows (2001)
Massoud Pedram ACM Distinguished Member (2008)
Ali Pinar ACM Distinguished Member (2015)
ACM Senior Member (2011)
Martha Pollack ACM Fellows (2011)
Dhiraj Pradhan ACM Fellows (1999)
Viktor Prasanna ACM Fellows (2007)
Sreeranga P Rajan ACM Distinguished Member (2014)
Bantwal R Rau ACM Fellows (2002)
ACM-IEEE CS Eckert-Mauchly Award (2002)
Sartaj K Sahni ACM Karl V. Karlstrom Outstanding Educator Award (2003)
ACM Fellows (1996)
Karem Sakallah ACM Fellows (2012)
Alberto Luigi Sangiovanni Vincentelli ACM Fellows (2014)
Sachin S. Sapatnekar ACM Fellows (2016)
Robert Schreiber ACM Fellows (2012)
ACM Distinguished Member (2006)
Sandeep K Shukla ACM Distinguished Member (2012)
ACM Senior Member (2007)
Anand Sivasubramaniam ACM Fellows (2017)
ACM Distinguished Member (2010)
ACM Senior Member (2009)
Peter James Stuckey ACM Distinguished Member (2009)
Donald E Thomas ACM Fellows (2007)
Mateo Valero ACM Distinguished Service Award (2012)
ACM-IEEE CS Eckert-Mauchly Award (2007)
ACM Fellows (2002)
Robert A. Walker Outstanding Contribution to ACM Award (2007)
ACM Distinguished Member (2006)
David Whalley ACM Distinguished Member (2009)
ACM Senior Member (2009)
Steve Wilton ACM Senior Member (2006)
Marilyn Claire Wolf ACM Fellows (2001)
Martin Wong ACM Fellows (2017)
Zeljko Zilic ACM Senior Member (2009)

First Name Last Name Paper Counts
Francky Catthoor 19
Irith Pomeranz 18
Krishnendu Chakrabarty 16
Nikil Dutt 15
Jason Cong 12
Partha Chakrabarti 11
Sheldon Tan 11
TingTing Hwang 9
Yunheung Paek 9
Sachin Sapatnekar 9
David Pan 8
Lei He 8
Bhargab Bhattacharya 8
Yaowen Chang 8
Evangeline Young 7
Spyros Tragoudas 7
Sule Ozev 7
Domenic Forte 7
Frank Vahid 7
Danny Wong 7
Luca Benini 7
Pallab Dasgupta 7
Massoud Pedram 7
Mark Tehranipoor 6
Alexandru Nicolau 6
MartindF Wong 6
Taewhan Kim 6
Sharad Malik 6
John Hayes 6
Jenqkuen Lee 6
Ryan Kastner 6
Jintai Yan 6
Andrew Kahng 6
Chengkok Koh 6
Sudhakar Reddy 6
Radu Marculescu 6
Igor Markov 6
Ali Dasdan 5
Xiaobosharon Hu 5
Iris Jiang 5
Soonhoi Ha 5
Ramesh Karri 5
Kiyoung Choi 5
Umit Ogras 5
Mahmut Kandemir 5
Hungming Chen 5
Kaushik Roy 5
Preeti Panda 5
Rajeev Kumar 5
Giovanni De Micheli 5
Aviral Shrivastava 5
Roman Lysecky 5
Nagarajan Ranganathan 5
Tony Givargis 5
Chungkuan Cheng 5
Chialin Yang 4
Rajesh Gupta 4
Jingyang Jou 4
Aarti Gupta 4
Chiuwing Sham 4
Pinghung Yuh 4
Enrico Macii 4
Ankur Srivastava 4
Peter Petrov 4
Peng Li 4
Twan Basten 4
Shihhsu Huang 4
Hans Wunderlich 4
Alex Jones 4
Yuanhao Chang 4
Sunyuan Hsieh 4
Martin Lukasiewycz 4
Allen Wu 4
Naehyuck Chang 4
Chang Liu 4
Jürgen Teich 4
Zili Shao 4
Sebastian Steinhorst 4
Miodrag Potkonjak 4
Wen Jone 4
Paul Gratz 4
Zoran Salcic 4
Dinesh Mehta 4
Jongeun Lee 4
Franco Fummi 4
Paulo Flores 4
Hai Zhou 4
Tsungyi Ho 4
Mehdi Tahoori 4
Zonghua Gu 4
Dirk Stroobandt 4
Azadeh Davoodi 4
Sunil Khatri 4
Zijiang Yang 4
Massimo Poncino 4
Kwangting Cheng 4
El Aboulhamid 4
Yinhe Han 3
Haibao Chen 3
Nicholas Zamora 3
Priyank Kalla 3
Elizabeth Rudnick 3
Dong Xiang 3
Dimitrios Soudris 3
Jun Yang 3
Yiping You 3
Baris Taskin 3
Sanghamitra Roy 3
Li Wang 3
Krishnendu Chakrabarty 3
Waikei Mak 3
Xianlong Hong 3
Hao Yu 3
Shihchieh Chang 3
Teiwei Kuo 3
Luigi Carro 3
Angeliki Kritikakou 3
Seda Memik 3
Chakkuen Wong 3
Akash Kumar 3
George Constantinides 3
Greg Stitt 3
Koushik Chakraborty 3
Avinash Malik 3
Praveen Raghavan 3
Swarup Bhunia 3
Dimitrios Kagaris 3
Dian Zhou 3
Henk Corporaal 3
Diana Marculescu 3
Yuan Xie 3
Viktor Prasanna 3
Karel Bruneel 3
Bijan Alizadeh 3
Valeria Bertacco 3
PAOLO Prinetto 3
Axel Jantsch 3
Jinyong Lee 3
Guangming Wu 3
Ronald Blanton 3
Xuan Zeng 3
Paoann Hsiung 3
Andrew Kennings 3
Yongje Lee 3
Kun Yang 3
Sreejit Chakravarty 3
Francisco Cazorla 3
Hamid Sarbazi-Azad 3
Alain Girault 3
Guy Gogniat 3
Prabhat Mishra 3
Sudip Roy 3
Dipankar Das 3
Sisira Panda 3
Masanori Kurimoto 3
Anna Bernasconi 3
Samarjit Chakraborty 3
Ali Afzali-Kusha 3
Xiaoyu Song 3
Ingoo Heo 3
Yuchin Hsu 3
Ozcan Ozturk 3
Bei Yu 3
Janet Roveda 3
Yunsi Fei 3
Peng Li 3
Peter Cheung 3
Valentina Ciriani 3
Arnout Vandecappelle 3
Shiyu Huang 3
Chenjie Yu 3
Chungwen Huang 3
Costas Goutis 3
Youngsoo Shin 3
Karem Sakallah 3
Fadi Kurdahi 3
Soheil Ghiasi 3
Seongnam Kwon 3
Gianpiero Cabodi 3
Juan Maestro 3
Kurt Keutzer 3
Sarma Vrudhula 3
Chunjason Xue 3
Jaume Abella 3
Pai Chou 3
Paul Bogdan 3
Alberto Sangiovanni-Vincentelli 3
Thambipillai Srikanthan 3
Partha Roop 3
Madhu Mutyam 3
Ozgur Sinanoglu 3
Yi Wang 3
Pedro Reviriego 3
Xiangrong Zhou 3
Daniel Gajski 3
Per Kjeldsberg 3
José Monteiro 3
Martin Palkovič 3
Yowtyng Nieh 3
Janak Patel 3
Saojie Chen 3
Mohammad Arjomand 3
David Atienza 3
Majid Sarrafzadeh 3
Shuvra Bhattacharyya 3
Hai Wang 3
Edwin Sha 3
Dawei Chang 2
Chung Tsao 2
Peichen Pan 2
Yiyu Shi 2
Yvon Savaria 2
Xin Yuan 2
Murali Jayapala 2
Kun Yuan 2
Sandeep Shukla 2
Kaihui Chang 2
Rajdeep Mukhopadhyay 2
Arcot Sowmya 2
Xin Fu 2
Manfred Glesner 2
Jim Holt 2
Magdy Abadir 2
Chandra Suresh 2
Heejong Park 2
ChengHsing Yang 2
Marco Murciano 2
Eduard Cerny 2
Youtao Zhang 2
Yuliang Wu 2
Christophe Wolinski 2
Ramin Bashizade 2
Shiyan Hu 2
Bo Yang 2
Seonwook Kim 2
Guoyong Shi 2
Rudy Lauwereins 2
Maria Michael 2
Bo Zhao 2
Sujit Dey 2
Nima Darav 2
Laleh Behjat 2
Gong Chen 2
Shigetoshi Nakatake 2
Ismail Kadayif 2
Kyumyung Choi 2
Maurizio Rebaudengo 2
Deepak Mathaikutty 2
Ayse Coskun 2
Siddhartha Mukhopadhyay 2
Russell Tessier 2
Andreas Dandalis 2
Seungcheol Baek 2
Chrysostomos Nicopoulos 2
Mingsong Chen 2
I Tseng 2
Alper Sen 2
Zebo Peng 2
Chrystian Guth 2
Chiachun Tsai 2
Román Hermida 2
Duncan Walker 2
Natarajan Viswanathan 2
Andreas Burg 2
Farinaz Koushanfar 2
Inki Hong 2
Sivaram Gopalakrishnan 2
Wim Heirman 2
Tienfu Chen 2
Erik Brockmeyer 2
Gary Dispoto 2
Picheng Hsiu 2
Naiwen Chang 2
Luís Silveira 2
Muhammet Ozdal 2
B Rau 2
Bart Mesman 2
Massoud Pedram 2
Sreeranga Rajan 2
Yiyu Liu 2
Vivek Sarin 2
Hiroaki Inoue 2
Srikanth Venkataraman 2
Bocheng Lai 2
Rafal Baranowski 2
José Güntzel 2
Shenchih Tung 2
Mario López 2
Pochun Huang 2
Bin Liu 2
Ya Wang 2
Xin Li 2
A Trinadh 2
Seetal Potluri 2
Lei Li 2
Shmuel Wimer 2
Javed Absar 2
Peiwen Luo 2
Krzysztof Kuchcinski 2
Susmita Sur-Kolay 2
Wayne Wolf 2
Younlong Lin 2
C Shi 2
Benjamin Schafer 2
Janming Ho 2
Srinivas Katkoori 2
Leonid Mats 2
James Cain 2
Smita Bakshi 2
Srinivas Devadas 2
Levent Aksoy 2
Sudhakar Yalamanchili 2
Zhiwei Qin 2
Kiwook Kim 2
Sungmo Kang 2
Adnan Aziz 2
Korosh Vatanparvar 2
Xiaoping Hu 2
Poyuan Chen 2
Mehrdad Nourani 2
Željko Žilić 2
Stefano Quer 2
Kai Zhu 2
Abhijit Jas 2
Nur Touba 2
Mohammad Tehranipoor 2
Hongbing Fan 2
Junjuan Xu 2
Vasilios Kelefouras 2
Tajana Rosing 2
Michael Riepe 2
Shantanu Dutt 2
Yongpan Liu 2
Saraju Mohanty 2
Sungjoo Yoo 2
Sunggu Lee 2
Hiren Patel 2
Elaheh Bozorgzadeh 2
Hyunggyu Lee 2
Pascal Fradet 2
David Hély 2
Junji Sakai 2
Ansuman Banerjee 2
Avinoam Kolodny 2
Mary Irwin 2
Hsiangpang Li 2
Erik Marinissen 2
Genggeng Liu 2
Wenzhong Guo 2
José Mendías 2
Ronald Graham 2
Esteban Tlelo-Cuautle 2
Mike Lee 2
Renhai Chen 2
Edwin Sha 2
Marco Bekooij 2
Vigyan Singhal 2
Yungchih Chen 2
Vinita Vasudevan 2
Franjo Ivančić 2
Robert Walker 2
Qinru Qiu 2
Guolong Chen 2
Stan Liao 2
Michael Kochte 2
Waishing Luk 2
M Balakrishnan 2
Syingjyan Wang 2
Katherine Li 2
Cheng Wang 2
Tsungyi Ho 2
Jhihrong Gao 2
Seokhyeong Kang 2
Masahiro Fujita 2
Shahin Nazarian 2
Lihong Zhang 2
Jagannathan Ramanujam 2
Yongjoo Kim 2
Michel Auguin 2
Min Xu 2
Freek Verbeek 2
Vijaykrishnan Narayanan 2
Leyla Nazhandali 2
Luciano Lavagno 2
Dongsheng Ma 2
Swapna Dontharaju 2
Xuexin Liu 2
Yihlang Li 2
Chingren Lee 2
Swaminathan Narayanaswamy 2
Adam Teman 2
Shengguo Wang 2
Dongil Hwang 2
Kees Goossens 2
Konstantin Moiseev 2
Chinhsien Wu 2
Chao Wang 2
JoAnn Paul 2
Hafizur Rahaman 2
Sergio Nocco 2
Michael Hsiao 2
Zhiyu Zeng 2
Jun Zeng 2
Dakai Zhu 2
David Westwick 2
Anmol Mathur 2
Youngsun Han 2
Jochen Jess 2
Sarmishtha Ghoshal 2
Arnab Sarkar 2
Mehdi Kamal 2
Ulf Schlichtmann 2
Aiqun Cao 2
Haibo Zeng 2
Roberto Passerone 2
Jin Sun 2
Timothy Sherwood 2
Chiajui Hsu 2
José Pino 2
Adnan Bouakaz 2
Gregory Dimitroulakos 2
Meikang Qiu 2
Masato Edahiro 2
Jun Yang 2
Siddharth Garg 2
Nicola Bombieri 2
Jörg Henkel 2
Ranga Vemuri 2
Jun Gu 2
Melvin Breuer 2
Hyesoon Kim 2
Hui Liu 2
Guihai Yan 2
Peter Milder 2
Hai Wang 2
Mohammad Al Faruque 2
Noor Sk 2
Yunfeng Yang 2
Hai Zhou 2
Arnab Roy 2
Marc Boulé 2
Ricardo Reis 2
Xing Huang 2
Laungterng Wang 2
Jiping Liu 2
Chienchih Huang 2
Chinlong Wey 2
Jwu Chen 2
Ran Wang 2
Paul Thadikaran 2
Guangyu Chen 2
Mateo Valero 2
Steven Wilton 2
Radu Marculescu 2
Yiyu Shi 2
Puneet Gupta 2
Shihhao Hung 2
John Gough 2
Philipp Mundhenk 2
Graziano Pravadelli 2
Matthew Guthaus 2
Gustavo Wilke 2
Julien Schmaltz 2
Jingyang Jou 2
Vinicius Livramento 2
Srijan Kumar 2
Wayne Luk 2
P Chakrabarti 2
Francesco Poletti 2
Sheqin Dong 2
Dani Tannir 2
Markus Püschel 2
Sobhanbabu Ch 2
V Kamakoti 2
Changhao Yan 2
Qing Duan 2
Chiaming Chang 2
Donald Thomas 2
Doosan Cho 2
Miguel Miranda 2
Fei Su 2
Lipin Chang 2
Hsinhung Chen 2
Farid Najm 2
Matteo Reorda 2
S Ramesh 2
Guido Araújo 2
Meeta Srivastav 2
Kanupriya Gulati 2
Deming Chen 2
Marlin Mickle 2
Keesung Han 1
Nakwoong Eum 1
Michael Birbas 1
Sudheendra Kadri 1
Hyunjik Song 1
Junhee Yoo 1
Ernest Lampe 1
Ruth Bahar 1
Surendra Bommu 1
Richard Raimi 1
Shyhjye Jou 1
Jongwon Lee 1
Rico Backasch 1
Pengwen Chen 1
Chinchih Chang 1
Chengyen Lin 1
Sudhanshu Vyas 1
Guangyu Sun 1
Huazhong Yang 1
Rensong Tsay 1
Alexander Veidenbaum 1
Wei Li 1
Carlos Llanos 1
Gary Yeap 1
Qi Wang 1
Kai Huang 1
Alois Knoll 1
Erwan Raffin 1
Dennis Sylvester 1
Vissarion Ferentinos 1
Seyed Miremadi 1
Ali Mirtar 1
Karel Heyse 1
Peiyu Lee 1
Yibo Lin 1
Burcin Cakir 1
Qi Hua 1
Tayung Liu 1
Stéphane Rubini 1
Congming Gao 1
Qiao Li 1
Chenhsuan Lin 1
Michail Noltsis 1
Hokwon Kim 1
Hailong Yao 1
Aiman El-Maleh 1
Egor Sogomonyan 1
Wangqi Qiu 1
Zhuo Li 1
Chieh Changfan 1
Somsubhra Mondal 1
Qingxu Deng 1
Steven Bashford 1
Yier Jin 1
Shirshendu Das 1
Jan Allebach 1
Prasenjit Chakraborty 1
Ahish Somashekar 1
Dongwook Lee 1
Kuencheng Chiang 1
Zhong Wang 1
Gokul Kandiraju 1
Pierre Paulin 1
Gang Wang 1
Chris Ostler 1
Chelun Hsu 1
Fujiang Lin 1
Sungkwang Lee 1
Apostolos Kountouris 1
K Yuan 1
James Huggins 1
Claudio Passerone 1
Alfredo Benso 1
Jean Legat 1
Gaurav Dhiman 1
Chih Lin 1
Tao Feng 1
Syed Suhaib 1
Andrei Rădulescu 1
Sean Liu 1
Xiao Liu 1
Fatma Abouelella 1
Tom Davidson 1
Yumin Lee 1
Vahid Lari 1
Amit Singh 1
Kiamal Pekmestzi 1
Elisenda Roca 1
Wenjian Luo 1
Talal Bonny 1
Kyoungwoo Lee 1
Fangfang Li 1
Mark Yeary 1
Hai Lin 1
Marc Riedel 1
Rajkumar Raval 1
Sandro Rigo 1
Hasan Khalifeh 1
Fang Liu 1
Plamen Nikolov 1
Max Schultz 1
Yu Hu 1
Roberto Cordone 1
Ernest Kuh 1
Janusz Brzozowski 1
Eric Johnson 1
JingWei Lin 1
Eric Chio 1
Junyan Ren 1
Ralph Hasholzner 1
Nong Xiao 1
Stefan Hillebrecht 1
Jiantao Wang 1
Wei Jiang 1
Yu Liu 1
Shaz Qadeer 1
Harry Hoster 1
Bingsheng He 1
Marcela Zuluaga 1
Jennifer Kitchen 1
Joseph Ganley 1
Juan Hamers 1
Chinghwa Cheng 1
Martin Streubühr 1
Jens Gladigau 1
Michael Meredith 1
Brady Hunsaker 1
Kaige Yan 1
Qing Su 1
Patrick Schaumont 1
Ashok Halambi 1
Biswadeep Chatterjee 1
Marco Platzner 1
Maria Padilla 1
Salim Chowdhury 1
Xing Hu 1
Shuangchen Li 1
Yining Zhang 1
Pranav Ashar 1
Brett Meyer 1
Chunhan Chen 1
Yaoguang Wei 1
Cliff Sze 1
Seokhyun Lee 1
Alessandro Pinto 1
Alvise Bonivento 1
Tanja Van Achteren 1
I Hsu 1
Hokyoon Lee 1
Florent De Lamotte 1
Fulvio Corno 1
Xiaotao Chen 1
Cornelis Van Eijk 1
Bruno Rouzeyre 1
Jongeun Lee 1
Chita Das 1
Giovanni De Micheli 1
Rami Melhem 1
Choonseung Lee 1
Ronny Krashinsky 1
Antonis Papanikolaou 1
Tomas Pecenka 1
Lukáš Sekanina 1
Zdeněk Kotásek 1
Laurent Freund 1
Michael Münch 1
Mohammad Foroozannejad 1
Hassan Salamy 1
Yoan Lin 1
Unmesh Bordoloi 1
Petru Eles 1
Marcelo Johann 1
Qiuping Yi 1
Zili Shao 1
Hidehiro Takata 1
YannRue Lin 1
Yosinori Watanabe 1
Tero Rissa 1
Chris Bleakley 1
Hao Li 1
Janet Wang 1
Alexandro Baldassin 1
James Moscola 1
Young Cho 1
Enshou Chang 1
Steve Tjiang 1
Nagu Dhanwada 1
Olivier Sentieys 1
Robert Brayton 1
Chingyi Huang 1
Pascal Meinerzhagen 1
Ramprasath S 1
Yichung Chen 1
Wei Zhang 1
Chao Chen 1
Zhaori Bi 1
Hyungon Moon 1
Jiwon Seo 1
Frederik Vandeputte 1
Stelios Mamagkakis 1
Puneet Sharma 1
Jos Huisken 1
Arnab Sinha 1
Bhaskar Pal 1
Yuanfang Hu 1
Yubin Zhang 1
Justin Stander 1
Anshul Kumar 1
Swarup Das 1
Andrew Cassidy 1
Hua Xiang 1
Rina Panigrahy 1
E Mariatos 1
Dhiraj Pradhan 1
Chaowen Tzeng 1
Kueichung Chang 1
Jihsheng Shen 1
Joachim Anlauf 1
Sami Taktak 1
Jianli Zhuo 1
Xingguang Feng 1
Michele Malgeri 1
Peter Bertels 1
Xinping Zhu 1
Hsipin Ma 1
Bontae Koo 1
Bettina Braitling 1
Raminder Bajwa 1
Jhengsyun Yang 1
F Johnson 1
Yushih Su 1
Chaitali Chakrabarti 1
Rungbin Lin 1
Donald Gelosh 1
Dorothy Setliff 1
Stephen Blythe 1
Alain Pegatoquet 1
Ramin Hojati 1
Yuetsang Chen 1
Ankur Srivastava 1
Martin Leucker 1
Renjie Lee 1
Wenpin Tu 1
Frank Vahid 1
Qi Guo 1
Olivier Temam 1
Hakan Aydín 1
Gang Qu 1
Lokwon Kim 1
John Villasenor 1
Marjan Asadinia 1
Hamid Azad 1
Michio Komoda 1
Zhen Chen 1
Menghuan Wu 1
Shihhung Weng 1
Alan Coppola 1
Chakchung Cheung 1
Robert Rogenmoser 1
Shantanu Ganguly 1
Adolfo Palma-Rodriguez 1
Vivek Joshi 1
Seokhyeong Kang 1
Evangelos Eleftheriou 1
Thomas Griffin 1
Bradley Kiddie 1
Daniel Limbrick 1
Xin Huang 1
Selçuk Köse 1
Anche Cheng 1
Malgorzata Marek-Sadowska 1
Jason Oberg 1
Baolei Mao 1
Sam Bayless 1
Bojan Maric 1
Yifang Liu 1
Shengde Wang 1
Sylvain Clerc 1
Fabian Firmin 1
Xiongfei Liao 1
Antonio Garcia-Dopico 1
Marisa López-Vallejo 1
Prabal Basu 1
Jinyong Lee 1
Tiantao Lu 1
Siyu Yue 1
Bruce Childers 1
Jerry Backer 1
Karthick Parashar 1
Hans Cappelle 1
Shyamsundar Venkataraman 1
Andrea Enrici 1
Srinivas Patil 1
Prosenjit Gupta 1
Geneeu Jan 1
András Orbán 1
Charles Chiang 1
Walid Najjar 1
Partha Biswas 1
Bin Xiao 1
Lu Peng 1
Patrick Cuevas 1
Heike Wehrheim 1
G Fang 1
Wei Dong 1
Hassan Albalawi 1
Joan Del Castillo 1
Taehyun Kim 1
Jinku Kim 1
Lalatendu Behera 1
Derong Liu 1
Jun Ma 1
Yu Hu 1
Mojtaba Ebrahimi 1
Laurence Pierre 1
Youngsik Kim 1
Ishwar Parulkar 1
Panayiotis Alefragis 1
Wolfgang Nebel 1
P Bakliwal 1
Bertan Bakkaloglu 1
Jaeyung Jun 1
Sangho Yu 1
Sandeep Goel 1
Muhammad Nummer 1
Le Jin 1
Wenyao Xu 1
Jef Van Meerbergen 1
Rainer Leupers 1
Alain Darte 1
Sungwoo Hur 1
Ashok Jagannathan 1
Keheng Huang 1
Kan Xiao 1
Hossein Mehri 1
Rathish Jayabharathi 1
Laurence Yang 1
Changhao Yan 1
Rômulo De Oliveira 1
Kara Poon 1
Ismaïl Chabini 1
Yeanyow Hwang 1
Krishnan Srinivasan 1
Vijaykumar Ramamurthi 1
Qubo Hu 1
Feng Liu 1
Guojie Luo 1
Aysa Tabrizi 1
Youjip Won 1
P Bannerjee 1
Gagan Hasteer 1
Jing Zeng 1
William Davis 1
Jinsik Kim 1
Hadi Esmaeilzadeh 1
Saeed Shamshiri 1
Jef Meerbergen 1
Meihsiang Tsai 1
Yihuang Hung 1
Jürgen Teich 1
Rui Zheng 1
Liang Shi 1
Jianhua Li 1
Harikumar Somakumar 1
Rafael Castro-López 1
Jennifer Dworak 1
Nuno Alves 1
Andy Lambrechts 1
Jonathan Clarke 1
Michael Hazeltine 1
Ryan Ketner 1
Evangeline Young 1
Nalini Venkatasubramanian 1
Mark Greenstreet 1
Jingjou Tang 1
TungChieh Tsai 1
Srikanth Chandrasekaran 1
Sanghoon Kwak 1
John Backes 1
Tomtong Jing 1
Robi Dutta 1
Adam Kaplan 1
Amit Singh 1
Sharad Sinha 1
Peter Middelhoek 1
Gilles Sicard 1
Yangdong Deng 1
Yue Yu 1
Jia Di 1
Yuankun Xue 1
Junghee Lee 1
Yinchi Peng 1
Hsiangjen Tsai 1
Kenghao Yang 1
Yanzhi Wang 1
Orlando Moreira 1
Mohammad Azarbad 1
Luís Pinho 1
Qingling Zhao 1
Scott Brandt 1
Rui Santos 1
Suganth Paul 1
Yokesh Kumar 1
Dimitris Bakalis 1
Kurt Antreich 1
ChiShong Wang 1
Bipul Paul 1
Juan De Vicente 1
KunLin Tsai 1
Shanqjang Ruan 1
Péter Arató 1
Michel Israel 1
Norbert Wehn 1
Hiroyuki Tomiyama 1
Wooyoung Jang 1
Matin Hashemi 1
Haifeng Qian 1
Guilherme Flach 1
Yenlung Chen 1
Eamonn O'Toole 1
Xuandong Li 1
Maciek Kormicki 1
Mingxuan Yuan 1
Xiuqiang He 1
Murli Tirumala 1
Rei Akiyama 1
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Jason Cheatham 1
Mauricio Ayala-Rincón 1
Hannahhonghua Yang 1
Qiang Zhou 1
Alex Yakovlev 1
Yinlong Xu 1
Diederik Verkest 1
Dimin Niu 1
William Robinson 1
Lei Jiang 1
Brahim Al Farisi 1
James Harbin 1
Li Jiang 1
Shalu 1
Hai Wang 1
N Beohar 1
Shaochung Wang 1
Yuanshin Hwang 1
Andreas Emeretlis 1
Kyuhyun Choi 1
Leonardo Pereira-Santos 1
Hongxia Zhou 1
Johann Knechtel 1
Hakan Yalcin 1
Kumar Parthasarathy 1
Song Liu 1
Ge Yu 1
Javier Resano 1
Daniel Mozos 1
KuangCyun Hsiao 1
Peter Marwedel 1
Jinjun Xiong 1
David Berner 1
Calin Ciordas 1
Sehwan Kim 1
Peiyu Huang 1
Xijiang Lin 1
Moritz Schmid 1
Sandip Kundu 1
Ryan Cochran 1
Atsuto Hanami 1
Juyueh Lee 1
Weifeng He 1
Szuchi Wang 1
V Nair 1
Hai Lin 1
Shenghua Liu 1
Daniel Kroening 1
Carlos Fernández 1
Chris Bleakley 1
Hasan Arslan 1
Haibo Wang 1
Chunkai Wang 1
Chingyu Chin 1
Dejun Mu 1
Mohit Tiwari 1
Xueliang Li 1
Andrew DeOrio 1
Antara Ain 1
Shangping Ren 1
Hanbin Hu 1
Shuwen Deng 1
Shamik Saha 1
Yang Song 1
Chienchih Chen 1
Hokyoon Lee 1
Il Park 1
Ji Li 1
Hyunok Oh 1
Suhaib Fahmy 1
Kuanhsien Ho 1
Katrina Lu 1
Dimitris Nikolos 1
Weikai Cheng 1
Chuanjun Zhang 1
Hui Huang 1
Ingrid Verbauwhede 1
Robert Rinker 1
Ugur Sezer 1
Kathy Hayashi 1
Qixiao Liu 1
Jay Roy 1
Yuwei Wu 1
Ganesh Gingade 1
Victor Champac 1
Chunhao Kuo 1
Luís Arcaro 1
Daniel Mueller-Gritschneder 1
Mahmood Naderan-Tahan 1
Naran Sirisantana 1
Jinfeng Liu 1
Maurice Bruynooghe 1
Bruno Girodias 1
Youcef Bouchebaba 1
Gabriela Nicolescu 1
Swaroop Ghosh 1
Karam Chatha 1
Qingping Tan 1
Chang Xu 1
Peixin Li 1
Xiaoqing Xu 1
Wenchao Zhang 1
Shengxi Diao 1
Pangbo Wu 1
Ramachandran Venkatasubramanian 1
Jason Higgins 1
Wei Zhao 1
Sreejit Chakravarty 1
Hungyi Li 1
Vladimir Zolotov 1
Stefano Quer 1
Frank Hannig 1
Yu Cao 1
Karthik Shankar 1
David Kolson 1
Philippe Grosse 1
Yves Durand 1
Owen Farell 1
Christoph Kern 1
Subhankar Mukherjee 1
Pallab Dasgupta 1
Ruijing Shen 1
Alan Mishchenko 1
Vinay Verma 1
Jongman Kim 1
Celina Val 1
Maria García 1
Li Shang 1
Zhuo Feng 1
Santiago Rodríguez 1
Xiaojian Yang 1
Stefan Obenaus 1
Kambiz Samadi 1
Vinson Young 1
Jongman Kim 1
Jeffrey Draper 1
Hazem Ali 1
Ioannis Latifis 1
Christakis Lezos 1
Karin Avnit 1
Sudeep Pasricha 1
Yuru Hong 1
Kunhyuk Kang 1
Jun Chen 1
Saurabh Adya 1
Chichou Kao 1
Yehia Massoud 1
Qingfeng Zhuge 1
Sunil Chappidi 1
Prabhav Agrawal 1
Andrea Bonetti 1
Woocheol Cho 1
Muhammad Nadeem 1
Guoqing Chen 1
Liang Chen 1
Song Jin 1
Huawei Li 1
Swanwa Liao 1
Mukund Narasimhan 1
Weitsun Sun 1
Sanghyeon Baeg 1
Sungkyu Lim 1
Eddie Hung 1
Paul Pop 1
Traian Pop 1
Petru Eles 1
Nitin Chandrachoodan 1
Qingbo Wu 1
Dongha Jung 1
Kiyin Chang 1
Ian Parberry 1
Jinnshyan Wang 1
Fabrizio Lombardi 1
Luiz Dos Santos 1
Praveen Murthy 1
Luiz Santos 1
Rafael Moreno 1
Jay Brockman 1
Mario Leung 1
Ryan Rakib 1
YuHsin Kuo 1
Muhammad Pasha 1
Michael Glaß 1
Zhiying Wang 1
Jieun Lim 1
Nagesh Lakshminarayana 1
Bernd Becker 1
Kamyiu Lam 1
Chiawei Lee 1
Yi Zou 1
Kaijie Wu 1
Wennai Cheng 1
Yunchih Chang 1
Arne Meeuw 1
Taeyoung Kim 1
Vikas Vij 1
Jiang Hu 1
Giovanni Beltrame 1
Xingquan Li 1
Wenxing Zhu 1
Yupeng Li 1
Sourav Das 1
Wonje Choi 1
Robert Johnson 1
Stefan Gheorghita 1
Andreas Hansson 1
Prasenjit Basu 1
Chengan Chien 1
Joachim Falk 1
Chunghsiang Lin 1
Miad Faezipour 1
Byunghyun Lee 1
Ilia Polian 1
Ingjer Huang 1
Abusaleh Jabir 1
Andreas Raabe 1
Philipp Hartmann 1
George Viamontes 1
Vincenza Carchiolo 1
Niall O'Neill 1
Alessandro Bogliolo 1
Jun Lu 1
Ashish Gupta 1
Hungming Chen 1
Christian Schulte 1
Songbin Pan 1
Brian Tagiku 1
Bailey Miller 1
Zhihua Zhou 1
Dennis Huang 1
Chungkuan Cheng 1
Dong Lee 1
Nobuhiro Tsuda 1
Arijit Ghosh 1
C Krishna 1
Zainalabedin Navabi 1
John Emmert 1
Jinian Bian 1
Haikun Zhu 1
Nizar Dahir 1
Terrence Mak 1
Jianhua Li 1
Liang Shi 1
David Blaauw 1
ChunDa Du 1
Cong Xu 1
Shimeng Yu 1
Stavros Hadjitheophanous 1
Yingchi Li 1
Mohammad Samavatian 1
Anand Raghunathan 1
Weikang Qian 1
Mustafa Canbolat 1
Ananya Singla 1
Alan Su 1
S Roy 1
George Theodoridis 1
Dana Price 1
Xiang Lu 1
Fernanda De Lima 1
Chien Liu 1
Nastaran Baradaran 1
Andreas Hoffmann 1
Scott Mahlke 1
Amit Chowdhary 1
John Lillis 1
João Marques-Silva 1
Richard Lasslop 1
Avaneendra Gupta 1
Kedar Namjoshi 1
George Kornaros 1
Jens Vygen 1
Qing Wu 1
Chen Huang 1
Joonho Kong 1
Jiliang Zhang 1
Eddie Cheng 1
Kamel Beznia 1
Ahcéne Bounceur 1
Franz Franchetti 1
Jun Matsushima 1
Shigeki Ohbayashi 1
Pengchih Wang 1
Yumin Kuo 1
Érika Cota 1
Marcelo Lubaszewski 1
Arun Kejariwal 1
Ilya Issenin 1
Daniel Blakely 1
Reiner Hartenstein 1
Yuke Wang 1
Fei Xia 1
Rajib Nath 1
Christian Buckl 1
Yenjen Chang 1
Wei Wang 1
MingChing Lu 1
Thanos Stouraitis 1
Mineo Kaneko 1
Haralampos Pozidis 1
Andrew Walls 1
Siva Boga 1
Vassos Soteriou 1
Ngai Wong 1
Minsu Kim 1
Ismail Bustany 1
Wuxi Li 1
Shounak Dhar 1
Yanan Sun 1
Philipp Ittershagen 1
Hengyang Zhao 1
M Shafiee 1
Jalil Boukhobza 1

Affiliation Paper Counts
Nanjing University of Science and Technology 1
University of Udine 1
Lahore University of Management Sciences 1
Air Force Research Laboratory 1
University of Central Florida 1
University of Ioannina 1
International Medical Equipment Collaborative 1
Tampere University of Technology 1
Karlsruhe Institute of Technology, Campus South 1
Nan-Tai Institute of Technology 1
INRIA Institut National de Rechereche en Informatique et en Automatique 1
Oakland University 1
Winbond Electronics Corporation 1
City University of New York 1
Lancaster University 1
Kwangwoon University 1
Indian Institute of Management Calcutta 1
Bahcesehir University 1
Toshiba America Research, Inc 1
FZI Research Computer Science Research Center Karlsruhe 1
Wuhan University 1
Intel Development Center, Israel 1
Shandong University 1
University at Buffalo, State University of New York 1
Naval Postgraduate School 1
University of St. Thomas, Minnesota 1
St. Louis University 1
CSIC - Instituto de Investigacion en Inteligencia Artificial 1
University of South Carolina 1
State University of Rio Grande do Sul 1
National Taipei University 1
Universite de Strasbourg 1
Advanced Micro Devices, Inc. 1
University of Kansas 1
Indian Institute of Technology, Bombay 1
Henan University of Science and Technology 1
Samsung Group 1
Siemens AG 1
Thomson, SA 1
University of New Brunswick 1
Mississippi State University 1
Global Unichip 1
Washington State University Tri-Cities 1
Facebook, Inc. 1
Tianjin University 1
Griffith University 1
Czech Technical University in Prague 1
Aalto University 1
The University of North Carolina System 1
Concordia University, Montreal 1
Jundi Shapur University of Dezful 1
Rensselaer Polytechnic Institute 1
Russian Academy of Sciences 1
North Dakota State University 1
Oracle Corporation 1
Kung Shan Institute of Technology 1
Commissariat a L'Energie Atomique CEA 1
Texas Instruments (India) Ltd 1
University of Akron 1
University of Oldenburg 1
National Institute of Technology, Durgapur 1
Capital Normal University China 1
STMicroelectronics Ltd - Bristol 1
San Francisco State University 1
University of Bridgeport 1
Nortel Networks 1
Oregon State University 1
Microsoft Research 1
University of Potsdam 1
Google Inc. 1
The University of North Carolina at Chapel Hill 1
Juniper Networks, Inc. 1
National Taiwan Ocean University 1
National Pingtung University 1
Rutgers, The State University of New Jersey 1
University of Idaho 1
Macau University of Science and Technology 1
LSI Corporation 1
Missouri University of Science and Technology 1
University of Kent 1
SUNY Brockport 1
Institute for Information Industry Taiwan 1
Colorado State University 1
National Ilan University Taiwan 1
P. A. College of Engineering 1
Bowling Green State University 1
Florida State University 1
Hitachi America, Ltd. 1
United States Air Force Institute of Technology 1
Kent State University 1
China National Petroleum Corporation 1
Beijing University of Chemical Technology 1
University of Colorado at Boulder 1
Ecole Normale Superieure de Lyon 1
Huawei Technologies Co., Ltd. 1
Taiwan Semiconductor Manufacturing Company 1
Federal University of Santa Maria 1
Silicon Graphics, Inc. 1
National Chi Nan University 1
University of Manchester 1
Oak Ridge National Laboratory 1
Yahoo Inc. 1
University of Nebraska - Lincoln 1
Kettering University 1
Iranian Research Institute for Fundamental Sciences 1
Centro de Investigaciones Energeticas, Medioambientales y Tecnologicas 1
Zenasis Technologies, Inc. 1
Institute of Computing Technology Chinese Academy of Sciences 1
University of Texas System 1
Valparaiso University 1
Gonzaga University 1
North Carolina Agricultural and Technical State University 1
Royal Military College of Canada 1
DoCoMo Communications Laboratories Europe GmbH 1
Miami University Oxford 1
King Abdullah University of Science and Technology 1
Lawrence Berkeley National Laboratory 1
Universite de Toulouse 1
University of Virginia 1
University of Kaiserslautern 1
International Institute of Information Technology, Kolkata 1
Wilfrid Laurier University 1
Ecole Centrale Marseille 1
Synopsys (India) Pvt. Ltd. 1
Catholic University of Pelotas 1
Myongji University 1
Spanish National Research Council 1
University of New Orleans 1
Universite de Lyon 1
University of Trento 1
Faraday Technology Corporation 1
Curtin University of Technology, Perth 1
MediaTek Inc 1
Fu Jen Catholic University 1
Robert Bosch GmbH 1
School of Higher Technology - University of Quebec 1
Oxford Brookes University 1
Asyst Technologies, Inc. 1
Intel Technology India Pvt Ltd. 1
Universite de Bretagne-Sud 1
University of Maryland, Baltimore County 1
North China Electric Power University 1
Vienna University of Technology 1
INRIA Rhone-Alpes 1
France Telecom 1
Texas State University-San Marcos 1
McMaster University 1
Clarkson University 1
Saint Francis Xavier University 1
Northrop Grumman corporation 1
Providence University Taiwan 1
The University of Warwick 1
Mindspeed Technologies 1
Cornell University 1
Yonsei University 1
Indian Institute of Technology, Kanpur 1
Auburn University 1
Kyungil University 2
George Mason University 2
Silesian Polytechnic University, Gliwice 2
University of Tokyo 2
National Key Laboratory for Parallel and Distributed Processing 2
Wright State University 2
Michigan State University 2
Texas A and M University System 2
CNRS Centre National de la Recherche Scientifique 2
East China Normal University 2
National Semiconductor Corporation 2
Altera Corporation 2
Radboud University Nijmegen 2
Daegu University 2
Technical University of Crete 2
Osaka University 2
Xidian University 2
University of Southampton 2
Universidad Autonoma de Barcelona 2
University of Cantabria 2
American University of Beirut 2
University of York 2
Realtek Semiconductor Corp. 2
Lebanese American University 2
University of Tubingen 2
Hefei University of Technology 2
Mentor Graphics Corporation 2
University of Twente 2
Columbia University 2
Khalifa University 2
IBM Research 2
Democritus University of Thrace 2
University of Southern California, Information Sciences Institute 2
Feng Chia University 2
National Taipei University of Technology 2
The University of North Carolina at Charlotte 2
University of Ferrara 2
Villanova University 2
University of Toronto 2
University of Lethbridge 2
Southern Illinois University 2
NYU Tandon School of Engineering 2
Kyushu University 2
Open University of the Netherlands 2
Sandia National Laboratories, New Mexico 2
Binghamton University State University of New York 2
University of Oxford 2
University of Washington, Seattle 2
Institute for Research in IT and Random Systems 2
University of Calcutta 2
King Fahd University of Petroleum and Minerals 2
Washington University in St. Louis 2
AT&T Inc. 2
Oldenburger Forschungs- Und Entwicklungsinstitut fur Informatik-Werkzeuge Und -Systeme 2
Japan Advanced Institute of Science and Technology 2
Universite d' Evry Val d'Essonne 2
Lund University 2
Southern Methodist University 2
Virginia Commonwealth University 2
University of Denver 2
Chengdu University of Information Technology 2
Indian Institute of Technology Hyderabad 2
Avant Corporation 2
Infineon Technologies AG 2
Universidad Autonoma de Madrid 2
University of Queensland 2
Brno University of Technology 2
Nokia Corporation 2
Beihang University 2
Illinois Institute of Technology 2
Cyprus University of Technology 2
Vanderbilt University 2
Budapest University of Technology and Economics 3
University of Oklahoma 3
Delft University of Technology 3
Hong Kong University of Science and Technology 3
Boston University 3
Bilkent University 3
Hunan University 3
University of Brasilia 3
Case Western Reserve University 3
Instituto Nacional de Astrofisica Optica y Electronica 3
NXP Semiconductors 3
Tunghai University 3
Cisco Systems 3
National Sun Yat-Sen University Taiwan 3
University of Catania 3
University of Melbourne 3
Michigan Technological University 3
Xilinx Inc. 3
Bar-Ilan University 3
Laboratoire Traitement et Communication de l'Information 3
Catholic University of Louvain, Louvain-la-Neuve 3
University of California System 3
Bogazici University 3
Memorial University of Newfoundland 3
Portland State University 3
CSIC-USE-Instituto de Microelectronica de Sevilla 3
University of Pisa 3
Global Foundries, Inc. 3
Stony Brook University 3
The University of Hong Kong 3
University of Dublin, Trinity College 3
SK Hynix Inc. 3
University of Victoria 3
Northeastern University China 3
Technical University of Dresden 3
Northwestern Polytechnical University China 4
Politecnico di Milano 4
University of Houston 4
Kitakyushu University 4
University of Texas at San Antonio 4
University College Dublin 4
Hanyang University 4
University of Peloponnese 4
University of Paderborn 4
Nanhua University Taiwan 4
Canakkale 18th March University 4
Macronix International Co 4
Motorola 4
Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA) 4
Laboratoire des Sciences et Techniques de l'Information, de la Communication et de la Connaissance 4
Hewlett-Packard Inc. 4
Motorola Austin 4
Sunchon National University 4
IBM Austin Research Laboratory 4
Peking University 4
Swiss Federal Institute of Technology, Zurich 4
University of Milan 4
Pohang University of Science and Technology 4
University of Cyprus 4
University of Arkansas - Fayetteville 4
TU Dortmund University 4
New York University Abu Dhabi 5
University of Tennessee Space Institute 5
Agilent Technologies 5
Technical University of Madrid 5
RWTH Aachen University 5
Louisiana State University 5
Rice University 5
New York University 5
University of Cincinnati 5
IBM Zurich Research Laboratory 5
Technical University of Darmstadt 5
Electronics Telecommunication Research Institute 5
Instituto Superior Tecnico 5
University of New South Wales 5
Fujitsu America, Inc. 5
Indian Institute of Engineering Science and Technology, Shibpur, Howrah, India 5
Qualcomm Incorporated 5
Chongqing University 5
Norwegian University of Science and Technology 5
Syracuse University 5
Indian Institute of Technology Roorkee 5
University of North Texas 5
Microsoft Corporation 5
Universite de Bretagne Occidentale 5
STMicroelectronics 5
Kyushu Institute of Technology 5
Western Michigan University 5
University of Bristol 5
Philips Research 5
Industrial Technology Research Institute of Taiwan 6
Nebrija University 6
City University of Hong Kong 6
National Technical University of Athens 6
University of Illinois 6
Sogang University 6
Universite Nice Sophia Antipolis 6
Chung Hua University 6
Northeastern University 6
Universidade de Lisboa 6
University of California, Davis 6
Magma Design Automation, Inc. 6
Holst Centre 6
Brown University 6
Universite de Rennes 1 6
University of Verona 6
North Carolina State University 6
Royal Institute of Technology 7
Washington State University Pullman 7
Linkoping University 7
Barcelona Supercomputing Center 7
Technion - Israel Institute of Technology 7
HP Labs 7
National University of Singapore 7
Instituto de Engenharia de Sistemas e Computadores Investigacao e Desenvolvimento em Lisboa 7
State University of Campinas 7
IBM Thomas J. Watson Research Center 7
National Taiwan University of Science and Technology 7
Massachusetts Institute of Technology 7
University of Minnesota System 7
University of Calgary 8
University of Wisconsin Madison 8
Iowa State University 8
National Chung Hsing University 8
Zhejiang University 8
University of California, Santa Cruz 8
Nanyang Technological University 8
Texas Instruments 8
Ulsan National Institute of Science and Technology 8
Indian Institute of Technology, Delhi 8
McGill University 9
University of Illinois at Chicago 9
University of Montreal 9
University of Connecticut 9
University of Michigan 9
Nanjing University 9
Drexel University 9
Freescale Semiconductor 9
Polytechnic School of Montreal 9
University of Electronic Science and Technology of China 9
National Central University Taiwan 9
Northwestern University 9
University of Freiburg 9
Indian Institute of Technology, Guwahati 9
Swiss Federal Institute of Technology, Lausanne 9
University of Bonn 9
Southern Illinois University at Carbondale 10
Korea University 10
The University of British Columbia 10
Chung Yuan Christian University 10
Karlsruhe Institute of Technology 10
NEC Laboratories America, Inc. 10
University of Stuttgart 10
University of Iowa 10
Stanford University 10
University of Minnesota Twin Cities 10
NEC Corporation 10
Broadcom Limited, San Jose 10
Federal University of Santa Catarina 11
Fuzhou University 11
Imperial College London 11
University of Utah 11
University of Bologna 11
University of Massachusetts Amherst 11
National University of Defense Technology China 12
Universite Grenoble Alpes 12
Korea Advanced Institute of Science & Technology 12
University of Notre Dame 13
Utah State University 13
Indian Statistical Institute, Kolkata 13
Princeton University 13
Yuan Ze University 13
University of Waterloo 13
Complutense University of Madrid 14
University of Auckland 14
Technical University of Munich 14
Samsung Electronics Co. Ltd. 14
Academia Sinica Taiwan 14
University of Science and Technology of China 14
Federal University of Rio Grande do Sul 15
University of South Florida Tampa 15
National Chung Cheng University 15
Indian Institute of Technology, Madras 15
University of California, Berkeley 15
University of Patras 15
Fudan University 15
Renesas Electronics Corporation 15
TUMCREATE Limited 16
Sharif University of Technology 16
Chinese Academy of Sciences 16
Hong Kong Polytechnic University 17
Shanghai Jiaotong University 17
Catholic University of Leuven, Leuven 17
University of Arizona 17
Ghent University 18
University of Tehran 18
University of Erlangen-Nuremberg 19
University of Texas at Dallas 19
Virginia Tech 20
Cadence Design Systems 20
Pennsylvania State University 21
Georgia Institute of Technology 21
University of California, Santa Barbara 21
University of Illinois at Urbana-Champaign 23
National Cheng Kung University 25
University of Florida 26
University of Southern California 27
Tsinghua University 28
University of Maryland 28
Eindhoven University of Technology 28
Arizona State University 28
Synopsys Incorporated 29
Chinese University of Hong Kong 31
University Michigan Ann Arbor 32
Interuniversity Micro-Electronics Center at Leuven 35
Duke University 36
Polytechnic Institute of Turin 37
Intel Corporation 39
Carnegie Mellon University 43
National Taiwan University 44
University of Pittsburgh 44
University of Texas at Austin 45
Purdue University 45
University of California, Riverside 46
University of California, San Diego 49
Texas A and M University 51
Indian Institute of Technology, Kharagpur 56
National Chiao Tung University Taiwan 60
University of California, Los Angeles 65
University of California, Irvine 67
National Tsing Hua University 73
Seoul National University 80

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Advances in Physical Design Automation and Regular Papers

Volume 23 Issue 4, July 2018 Special Section on Advances in Physical Design Automation and Regular Papers
Volume 23 Issue 3, April 2018
Volume 23 Issue 2, January 2018

Volume 23 Issue 1, October 2017
Volume 22 Issue 4, July 2017
Volume 22 Issue 3, May 2017
Volume 22 Issue 2, March 2017 Special Section of IDEA: Integrating Dataflow, Embedded Computing, and Architecture

Volume 22 Issue 1, December 2016
Volume 21 Issue 4, September 2016
Volume 21 Issue 3, July 2016 Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers
Volume 21 Issue 2, January 2016

Volume 21 Issue 1, November 2015
Volume 20 Issue 4, September 2015 Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems
Volume 20 Issue 3, June 2015
Volume 20 Issue 2, February 2015

Volume 20 Issue 1, November 2014
Volume 19 Issue 4, August 2014
Volume 19 Issue 3, June 2014
Volume 19 Issue 2, March 2014

Volume 19 Issue 1, December 2013
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