ACM Transactions on

Design Automation of Electronic Systems (TODAES)

Latest Articles

Distributed Machine Learning on Smart-Gateway Network toward Real-Time Smart-Grid Energy Management with Behavior Cognition

Real-time data analytics for smart-grid energy management is challenging with consideration of both... (more)

A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

Side-channel attacks are a prominent threat to the security of embedded systems. To perform them, an... (more)

Non-Intrusive In-Situ Requirements Monitoring of Embedded System

Accounting for all operating conditions of a system at the design stage is typically infeasible for complex systems. Monitoring and verifying system... (more)

Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences

Earlier works observed that certain primary inputs have preferred values, which help increase the... (more)

Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip

Three-dimensional (3D) integration enables the design of high-performance and energy-efficient network on chip (NoC) architectures as communication... (more)

Folded Circuit Synthesis: Min-Area Logic Synthesis Using Dual-Edge-Triggered Flip-Flops

The area required by combinational logic of a sequential circuit based on standard flip-flops can be reduced by identifying subcircuits that are identical. Pairs of matching subcircuits can then be replaced by circuits in which dual-edge-triggered flip-flops operate on multiplexed data at the rising and falling edges of the clock signal. We show... (more)

Guiding Formal Verification Orchestration Using Machine Learning Methods

Typical modern HW designs include many blocks associated with thousands of design properties. Having today's commercial formal verifiers... (more)

An Algorithmic Approach to Formally Verify an ECC Library

The weakest link in cryptosystems is quite often due to the implementation rather than the mathematical underpinnings. A vast majority of attacks in... (more)

Enhancing Flash Memory Reliability by Jointly Considering Write-back Pattern and Block Endurance

Owing to high cell density caused by the advanced manufacturing process, the reliability of flash... (more)

Toward Effective Reliability Requirement Assurance for Automotive Functional Safety

Automotive functional safety requirement includes response time and reliability requirements learning from the functional safety standard ISO 26262.... (more)

GPlace3.0: Routability-Driven Analytic Placer for UltraScale FPGA Architectures

Optimizing for routability during FPGA placement is becoming increasingly important, as failure to spread and resolve congestion hotspots throughout the chip, especially in the case of large designs, may result in placements that either cannot be routed or that require the router to work excessively hard to obtain success. In this article, we introduce a new, analytic routability-aware placement algorithm for Xilinx UltraScale FPGA architectures. The proposed algorithm, called GPlace3.0, seeks to optimize both wirelength and routability. Our work contains several unique features including a novel window-based procedure for satisfying legality constraints in lieu of packing, an accurate... (more)


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Forthcoming Articles
Data-driven Anomaly Detection with Timing Features for Embedded Systems

Malware is a serious threat to network-connected embedded systems, as evidenced by the continued and rapid growth of such devices, commonly referred to as of the Internet of Things. Their ubiquitous use in critical applications require robust protection to ensure user safety and privacy. That protection must be applied to all system aspects, extending beyond protecting the network and external interfaces. Anomaly detection is one of the last lines of defence against malware, in which data-driven approaches that require the least domain knowledge are popular. However, embedded systems, particularly edge devices, face several challenges in applying data-driven anomaly detection, including unpredictability of malware, limited tolerance to long data collection windows, and limited computing/energy resources. In this paper, we utilize subcomponent timing information of software execution, including intrinsic software execution, instruction cache misses, and data cache misses as features, to detect anomalies based on ranges, multidimensional Euclidean distance, and classification at runtime. Detection methods based on lumped timing range are also evaluated and compared. We design several hardware detectors implementing these data-driven detection methods, which non-intrusively measuring lumped/subcomponent timing of all system/function calls of the embedded application. We evaluate the area, power, and detection latency of the presented detector designs. Experimental results demonstrate that the subcomponent timing model provides sufficient features to achieve high detection accuracy with low false positive rates using a one-class support vector machine, considering sophisticated mimicry malware.

An approximation algorithm for threshold voltage optimization

We present a primal-dual approximation algorithm for minimizing the leakage power of an integrated circuit by assigning gate threshold voltages. While most existing techniques do not provide a performance guarantee, we prove an upper bound on the power consumption. The algorithm is practical and works with an industrial sign-off timer. It can be used for post-routing power reduction or for optimizing leakage power throughout the design flow. We demonstrate the practical performance on recent microprocessor units. Our implementation obtains significant leakage power reductions of up to 8% on top of one of the most successful algorithms for gate sizing and threshold voltage optimization. After timing-aware global routing we achieve leakage power reductions of up to 34%.

Editorial for TODAES Special Section on Internet of Things System Performance, Reliability, and Security

CASCA: a Design Automation Approach for Designing Hardware Countermeasures Against Side Channel Attacks

Implementing a cryptographic circuit poses challenges not always acknowledged in the backing mathematical theory. One of them is the vulnerability against \emph{side channel attacks}. A side channel attack is a procedure that uses information leaked by the circuit through, for example, its own power consumption or electromagnetic emissions, to derive sensitive data (e.g, the secret key used for encryption). Nowadays, we design circuitry to keep this sensitive information from leaking (i.e., a \emph{countermeasure}), but the path from specification down to implementation is far from being fully automatic. As we know, manual refinement steps can be error prone and the sheer potential of these errors can be devastating in a scenario such as the one we are dealing with. In this paper, we investigate whether a single embedded domain specific language (EDSL) can, at the same time, help us specifying and enforcing the functionality of the circuit as well as its protection against side-channel attacks. The EDSL is a fundamental block of an original design flow (named Countermeasure Against Side-Channel Attacks, i.e., CASCA) whose aim is to complement an existing industrial scenario and to provide the necessary guarantee that a secure primitive is not vulnerable up to a first order attack. As a practical case study, we will show how we applied the proposed tools to ensure both functional and extra-functional correctness of a composite-field AES S-Box.

Boundary-Functional Broadside and Skewed-Load Tests

Close-to-functional broadside tests are used for avoiding overtesting of delay faults that can result from non-functional operation conditions, while avoiding test escapes because of faults that cannot be detected under functional operation conditions. When a close-to-functional broadside test deviates from functional operation conditions, the deviation can affect the entire circuit. This paper defines the concept of a boundary-functional broadside test where non-functional operation conditions are prevented from crossing a preselected boundary. Using the procedure described in this paper, the boundary maintains the same values under a boundary-functional broadside test as under a functional broadside test from which it is derived. Indirectly, this ensures that the deviations from functional operation conditions throughout the entire circuit are limited. The concept of a boundary-functional broadside test is extended to skewed-load tests, and to partial-boundary-functional tests. Experimental results are presented for benchmark circuits to demonstrate the fault coverage improvements that can be achieved using boundary-functional broadside and skewed-load tests as well as partial-boundary-functional tests of both types.

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering

This paper presents a rigorous step towards design-for-assurance by introducing a new class of logically reconfigurable design resilient to design reverse engineering. Based on the non-volatile spin transfer torque (STT) magnetic technology, we introduce a basic set of non-volatile reconfigurable Look-Up-Table (LUT) logic components (NV-STT-based LUTs). STT-based LUT with significantly different set of characteristics compared to CMOS provides new opportunities to enhance design security yet makes it challenging to remain highly competitive with custom CMOS or even SRAM-based LUT in terms of power, performance and area. To address these challenges, we propose several algorithms to select and replace custom CMOS gates with reconfigurable STT-based LUTs during design implementation such that the functionality of STT based components and therefore the entire design cannot be determined in any manageable time, rendering any design reverse engineering attack ineffective. Our study conducted on a large number of standard circuit benchmarks concludes significant resiliency of hybrid STT-CMOS circuits against various types of attacks. Furthermore, the selection algorithms on average have a small impact on the performance of the circuit. We also tested these techniques against satisfiability attacks developed recently and show that these techniques also render more advanced reverse-engineering techniques computationally infeasible.

Optimal Allocation of Computation and Communication in an IoT Network

Internet of things (IoT) is being developed for a wide range of applications from home automation and personal fitness, to smart cities. With the extensive growth in adaptation of IoT devices, comes the uncoordinated and substandard designs aimed at promptly making products available to the end consumer. This substandard approach restricts the growth of IoT in the near future and necessitates studies to understand requirements for an efficient design. A particular area where IoT applications have grown significantly is the surveillance and monitoring. Applications of IoT in this domain are relying on distributed sensors, each equipped with a battery, capable of collecting images, processing images, and communicating the raw or processed data to the nearest node until it reaches the base station for decision making. In such an IoT network where processing can be distributed over the network, the important research question is how much of data each node should process and how much it should communicate for a given objective. This work answers this question and provides a deeper understanding of energy and delay trade-offs in an IoT network with three different target metrics.

SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks

Neural networks (NN) have achieved great success in a broad range of applications. As NN-based methods are often both computation and memory intensive, accelerator solutions have been proved to be highly promising in terms of both performance and energy efficiency. Although prior solutions can deliver high computational throughput for convolutional layers, they could incur severe performance degradation when accommodating the entire network model, because there exist very diverse computing and memory bandwidth requirements between convolutional layers and fully-connected layers, and furthermore, among different NN models. To overcome this problem, we proposed an elastic accelerator architecture, called SynergyFlow, which intrinsically supports layer-level and model-level parallelism for large-scale deep neural networks. Our design boosts the resource utilization by exploiting the complementary effect of resource demanding in different layers and different NN models. SynergyFlow can dynamically reconfigure itself according to the workload characteristics, maintaining a high performance and high resource utilization among various models. As a case study, we implement SynergyFlow on a P395-AB FPGA board. Under 100MHz working frequency, our implementation improves the performance by 33.8% on average (up to 67.2% on AlexNet) compared to comparable provisioned previous architectures.

Fault-Tolerant Unicast-Based Multicast for Reliable Network-on-Chip Testing

We present a unied test technique that targets faults in links, routers, and cores of a network-on- chip design based on test sessions. We call an entire procedure, that delivers test packets to the subset of routers/cores, a test session. Test packets for routers are delivered to them via the fault- free links and routers that were identied in the previous test sessions to avoid packet corruption. Test packet delivery for routers is implemented as a fault-tolerant unicast-based multicast scheme within the tested part of the network-on-chip. A new fault-tolerant routing algorithm is proposed for unicast-based multicast test delivery. Identical cores share the same test set, and they are tested within the same test session. Simulation results highlight the eectiveness of the proposed method in reducing test time.

Quality-Enhanced OLED Power Savings on Mobile Devices

In the future, mobile systems will increasingly feature more advanced organic light-emitting diode (OLED) displays. The power consumption of these displays is highly dependent on the image content. However, existing OLED power-saving techniques either change the visual experience of users or degrade the visual quality of images in exchange for a reduction in the power consumption. Some techniques attempt to enhance the image quality by employing a compound objective function. In this paper, we present a win-win scheme that always enhances the image quality while simultaneously reducing the power consumption.We define metrics to assess the benefits and cost for potential image enhancement and power reduction. We then introduce algorithms that ensure the transformation of images into their quality-enhanced power-saving versions. Next, the win-win scheme is extended to process videos at a justifiable computational cost. All the proposed algorithms are shown to possess the win-win property without assuming accurate OLED power models. Finally, the proposed scheme is realized through a practical camera application and a video camcorder on mobile devices. The results of experiments conducted on a commercial tablet with a popular image database and a smartphone with real-world videos are very encouraging and provide valuable insights for future research and practices.

Rapid Triggering Capability using an Adaptive Overlay during FPGA Debug

FPGA technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long design and debug cycles. To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required upon modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for trigger-type circuits. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40 seconds instead of recompiling the circuit during debug iterations, increasing debug productivity.

Harvesting Row-Buffer Hits via Orchestrated Last-Level Cache and DRAM Scheduling for Heterogeneous Multicore Systems

In heterogeneous multicore systems, the memory subsystem, including the last-level cache and DRAM, is widely shared among the CPU, the GPU, and the real-time cores. Due to their distinct memory traffic patterns, heterogeneous cores result in more frequent cache misses at the last-level cache. As cache misses travel through the memory subsystem, two schedulers are involved for the last-level cache and DRAM respectively. Prior studies treated the scheduling of the last-level cache and DRAM as independent stages. However, with no orchestration and limited visibility of memory traffic, neither scheduling stage is able to ensure optimal scheduling decisions for memory efficiency. Unnecessary precharges and row activations happen in DRAM when the memory scheduler is ignorant of incoming cache misses and DRAM row-buffer states are invisible to the last-level cache. In this paper, we propose a unified memory controller for the the last-level cache and DRAM with orchestrated schedulers. The memory scheduler harvests row-buffer hit opportunities in cache request buffers during spare time without inducing significant implementation cost. Extensive evaluations show that the proposed controller improves the total memory bandwidth of DRAM by 16.8% on average and saves DRAM energy by up to 29.7% while achieving comparable CPU IPC. In addition, we explore the potential of the proposed memory controller to attain improvements on both memory bandwidth and CPU IPC.

PV -Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this paper, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the operational efficiency. Our experimental results show that the proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.

SHAIP: Secure Hamming Distance for Authentication of Intrinsic PUFs

In this paper, we present SUMMA-PUF, a novel mutual authentication scheme that allows an unlimited number of authentication by employing a weak Physical Unclonable Function (PUF). PUFs are being increasingly used for remote authentication of devices. Among different variants, the intrinsic PUFs, which can be built with little or no modification of the underlying hardware, are most suitable for this task as most of these devices have limited resources. One major drawback of current authentication schemes is that they expose the PUF response and thus make the intrinsic PUFs, which have a limited number of challenge-response pairs, unusable after a certain number of authentication sessions. Moreover, these schemes are one way since they only allow one party, the prover, to authenticate itself to the verifier. We propose a mutual authentication scheme that allows both parties to authenticate to each other without revealing the PUF responses either from the PUF held at the remote device or from the CRP database held at the verifier end. The authentication is performed through secure function evaluation methods that allow two parties to jointly compute a function without revealing their respective inputs. We show that our scheme is effective with all state-of-the-art intrinsic PUFs. The proposed scheme is lightweight and does not require any modification to the underlying hardware.

P3: Privacy Preserving Positioning for Smart Automotive Systems

This paper presents the first provably secure localization method for smart automotive systems. Using this method, a car, lost due to unavailability of GPS, can compute its location with assistance from three nearby cars while the locations of all the participating cars including the lost car remain private. Technological enhancement of modern vehicles, especially in navigation and communication, necessitates parallel enhancement in security and privacy. Previous approaches to maintaining user location privacy suffered from one or more of the following drawbacks: trade-off between accuracy and privacy, one-sided privacy and need of a trusted third party that presents a single point to attack. The localization method presented here is one of the very first location-based services that eliminates all these drawbacks. Two protocols for computing the location is presented here based on two Secure Function Evaluation (SFE) techniques that allow multiple parties to jointly evaluate a function on inputs which are encrypted to maintain privacy. The first one is based on the two-party protocol named Yaos Garbled Circuit (GC). The three assisting cars participate in a total six invocations of the two-party GC operation to compute the location of the lost car without revealing their location to one another. The second one is based on only one invocation of the Beaver-Micali-Rogaway (BMR) protocol that allows inputs from more than two parties. The two secure localization protocols exhibit trade-offs between performance and resilience against collusion. Along with devising the protocols we design and optimize netlists for the functions required for computation of location by leveraging conventional logic synthesis tools with custom libraries optimized for SFE. Proof-of-concept implementation of the protocol shows that the complete operation can be performed within only 355 ms. The fast computing time enables localization of even moving cars.

Knowledge and Simulation Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test Applications

We propose a passive, fully-differential, synthesizable zoom-ADC architecture for BIST applications, along with a synthesis tool that can target various design specifications. We present the detailed ADC architecture and a step by step process designing the zoom-ADC. The design flow does not rely on extensive knowledge of an experienced ADC designer. Two ADCs have been synthesized with different performance requirements in 65nm CMOS process. The first ADC achieves 91dB SNR in 512¼s measurement time and consumes 14.95¼W power. The second design achieves 78.2dB SNR in 31.25¼s measurement time and consumes 60¼W power.

ERASMUS: Efficient Remote Attestation via Self-Measurement for Unattended Settings

Remote attestation (RA) is a popular means of detecting malware in embedded and IoT devices. RA is usually realized as an interactive protocol, whereby a trusted party  verifier  measures integrity of a potentially compromised remote device  prover. Early work focused on purely software-based and fully hardware-based techniques, neither of which is ideal for low-end devices. More recent results have yielded hybrid (SW/HW) security architectures comprised of a minimal set of features to support efficient and secure RA on low-end devices. All prior RA techniques require on-demand operation, i.e, RA is performed in real time. We identify some drawbacks of this general approach in the context of unattended devices: First, it fails to detect mobile malware that enters and leaves the prover between successive RA instances. Second, it requires the prover to engage in a potentially expensive (in terms of time and energy) computation, which can be harmful for critical or real-time devices. To address these drawbacks,we introduce the concept of self-measurement where a prover device periodically (and securely) measures and records its own software state, based on a pre-established schedule. A possibly untrusted verifier occasionally collects and verifies these measurements. We present the design of a concrete technique called ERASMUS: Efficient Remote Attestation via Self-Measurement for Unattended Settings, justify its features and evaluate its performance. In the process, we also define a new metric  Quality of Attestation (QoA). We argue that ERASMUS is well-suited for time-sensitive and/or safety-critical applications that are not served well by on-demand RA. Finally, we show that ERASMUS is a promising stepping stone towards handling attestation of multiple devices (i.e., a group or swarm) with high mobility.

Optimization of Fault-Tolerant Mixed-Criticality Multi-Core Systems with Enhanced WCRT Analysis

This paper proposes a novel optimization technique of fault-tolerant mixed-criticality multi-core systems with worst-case response time (WCRT) guarantees. Typically, in fault-tolerant multi-core systems, tasks can be replicated or re-executed in order to enhance the reliability. In addition, based on the policy of mixed-criticality scheduling, low-criticality tasks can be dropped at runtime. Such uncertainties caused by hardening and mixed-criticality scheduling make WCRT analysis very difficult. We show that previous analysis techniques are pessimistic as they consider avoidably extreme cases that can be safely ignored within the given reliability constraint. We improve the analysis in order to tighten the pessimism of WCRT estimates by considering the maximum number of faults to be tolerated. Further, we improve the mixed-criticality scheduling by allowing partial dropping of low-criticality tasks. On top of those, we explore the design space of hardening, task-to-core mapping, and quality-of-service of the multi-core mixed-criticality systems. The effectiveness of the proposed technique is verified by extensive experiments with synthetic and real-life benchmarks.

Automatic Optimization of the VLAN Partitioning in Automotive Communication Networks

Dividing the communication network into so-called virtual local area networks(VLANs), i.e., subnetworks which are isolated at the data link layer (OSI layer 2), is a promising approach to address the increasing security challenges in automotive networks. The automation of the VLAN partitioning is a well researched problem in the area of local or metropolitan area networks. However, the approaches used there are hardly applicable for the design of automotive networks as they mainly focus on reducing the amount of broadcast traffic and cannot capture the many design objectives of automotive networks like the message timing or the link load, which are affected by the VLAN partitioning. As a remedy, this article proposes a 0-1 ILP-based approach to generate a message routing which is feasible with respect to the VLAN-related routing restrictions in automotive networks. This approach can be used for a design space exploration to optimize not only the VLAN partitioning, but also other routing-related objectives. We demonstrate both the efficiency of our message routing approach and the now accessible optimization potential for the complete E/E architecture using a mixed-criticality system from the automotive domain.

Remote Detection of Unauthorized Activity via Spectral Analysis

Unauthorized hardware or firmware modifications, known as trojans, can steal information, drain the battery, or damage IoT devices. Since trojans may be triggered in the field at an unknown instance, it is important to detect their presence at run-time. However, it is difficult to run sophisticated detection algorithms on these devices due to limited computational power and energy, and in some cases lack of accessibility. This paper presents a stand-off self-referencing technique for detecting unauthorized activity. The proposed technique processes involuntary electromagnetic emissions on a separate hardware, which is physically decoupled from the device under test. When the device enters the test mode, it runs a predefined application repetitively with a fixed period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operating bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicates the presence of unknown (unauthorized) activity. Hence, we are able to differentiate trojan activity without using a golden reference, or any knowledge on the attributes of the trojan activity. Experiments based on hardware measurements show that the proposed technique achieves close to 100% detection accuracy at up to 120 cm distance.

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification

Modern Systems-on-Chip (SoC) designs are increasingly heterogeneous and contain specialized semi-programmable accelerators in addition to programmable processors. In contrast to the pre-accelerator era, when the ISA played an important role in verification by enabling a clean separation of concerns between software and hardware, verification of these accelerator-rich SoCs presents new challenges. From the perspective of hardware designers, there is a lack of a common framework for formal functional specification of accelerator behavior. From the perspective of software developers, there exists no unified framework for reasoning about software/hardware interactions of programs that interact with accelerators. This paper addresses these challenges by providing a formal specification and high-level abstraction for accelerator functional behavior. It formalizes the concept of an Instruction Level Abstraction (ILA), developed informally in our previous work on abstraction synthesis, and shows its application in modeling and verification of accelerators. This formal ILA extends the familiar notion of instructions to accelerators and provides a uniform, modular, and hierarchical abstraction for modeling software-visible behavior of both accelerators and programmable processors. We demonstrate the applicability of the ILA through several case studies of accelerators (for image processing, machine learning and cryptography), and a general-purpose processor (RISC-V). We show how the ILA model facilitates equivalence checking between two ILAs, and between an ILA and its hardware finite-state machine (FSM) implementation. Further, this equivalence checking supports accelerator upgrades using the notion of ILA compatibility, similar to processor upgrades using ISA compatibility.

Instinctive Assistive Indoor Navigation using Distributed Intelligence

The development of cyber-physical systems and the Internet of Things (IoT) have a signifcant potential to improve the eectiveness of assistive technologies for those with physical disabilities. To be practical, assistive systems should minimize the number of inputs from users, reducing cognitive and physical eort required. This paper presents a versatile, energy-efcient framework and algorithm for assistive indoor navigation using an electric wheelchair and user inputs from multiple modalities. The proposed algorithm automates indoor navigation using only a few user commands captured through a wearable device, with the goal of simplifying navigation tasks and making them more instinctive for the user. We evaluated the proposed methodology using both a virtual smart building and a prototype built with o-the-shelf IoT development boards. Our evaluations for three dierent oorplans show one order of magnitude reduction in user eort and communication energy required for navigation when compared with conventional navigation methodologies that require continuous user inputs.

Switching Predictive Control Using Reconfigurable State-Based Model

Advanced control methodologies have helped the development of modern vehicles that are capable of path planning and path following. For instance, Model Predictive Control (MPC) employs a predictive model to predict the behavior of the physical system for a specific time horizon in the future. An optimization problem is solved to compute optimal control actions while handling model uncertainties and nonlinearities. However, these prediction routines are computationally intensive and the computational overhead grows with the complexity of the model. \textit{Switching MPC} addresses this issue by combining multiple predictive models, each with a different precision granularity. In this paper, we proposed a novel switching predictive control method based on a model reduction scheme to achieve various model granularities for path following in autonomous vehicles. A state-based model with tunable parameters is proposed to operate as a reconfigurable predictive model of the vehicle. A run-time switching algorithm is presented that selects the best model using machine learning. We employed a metric that formulates the trade-off between the error and computational savings due to model reduction. Our simulation results show that the use of the predictive model in the switching scheme as opposed to single granularity scheme yields a 45% decrease in execution time in trade-off for a small 12% loss in accuracy in prediction of future outputs and no loss of accuracy in tracking the reference trajectory.

UCR: An Unclonable Environmentally-Sensitive Chipless RFID Tag For Protecting Supply Chain

Chipless Radio Frequency Identification (RFID) tags that do not include an integrated circuit (IC) in the transponder are more appropriate for supply chain management of low-cost commodities and have been gaining extensive attention due to their relatively lower price. However, existing chipless RFID tags consume considerable tag area and manufacturing time/cost because of complex fabrication process (e.g., requiring removing or shorting some resonators on the tag substrate to encode data). Worse still, their identifiers (IDs) are deterministic, clonable, and small in terms of bitwidth. To address these shortcomings and help preserve the cold chain for commodities (e.g., vaccines, pharmaceuticals, etc.) sensitive to temperature, we develop a novel unclonable environmentally-sensitive chipless RFID (UCR) tag that intrinsically generates a unique ID from both manufacturing variations and ambient temperature variation. UCR tag consists of two parts: (i) a certain number of concentric ring slot resonators integrated on a certain laminate (e.g., TACONIC TLX-0), whose resonance frequencies rely on slot geometric parameters and substrate dielectric constant that are sensitive to manufacturing variations; and (ii) a standalone circular ring slot resonator integrated on a particular substrate (e.g., grease) that will be melted at a high temperature, whose resonance frequency relies on geometric parameters of slot resonator, substrate dielectric constant, and ambient temperature. UCR tags have the capability to track commodities and their temperatures in the supply chain. The area of UCR tag is comparable to regular quick response (QR) code. Experimental results based on UCR tag prototypes have verified their uniqueness and reliability.

SystemC-AMS Thermal Modeling for the Co-simulation of Functional and Extra-Functional Properties

Temperature is a critical property of smart systems, due to its impact on reliability and to its inter-dependence with power consumption. Unfortunately, the current design flows evaluate thermal evolution ex-post, on offline power traces. This does not allow to consider temperature as a dimension in the design loop, and it misses all the complex inter-dependencies with design choices and power evolution. In this paper, by adopting the functional language SystemC-AMS, we propose a method to enable thermal/power/functional co-simulation. The system thermal model is built by using state-of-the-art circuit equivalent models, by exploiting the support for electrical linear networks intrinsic of SystemC-AMS. The experimental results will show that the choice of SystemC-AMS is a winning strategy for building a simultaneous simulation of multiple functional and extra-functional properties of a system. The generated code exposes an accuracy comparable to that of reference thermal simulator HotSpot. Additionally, the initial overhead due to the general purpose nature of SystemC-AMS is compensated by surprisingly high performance of transient simulation, with speedups as high as two orders of magnitude. The application of the proposed methodology to a set of benchmarks, used for the IEEE PATMOS design contest, will additionally prove the effectiveness of the SystemC-AMS thermal simulator.

Detection Mechanisms for Unauthorized Wireless Transmissions

With increasing diversity of supply chains from design to delivery, there is an increasing risk that unauthorized changes can be made within an IC. One of the motivations for this type of change is to learn important information (such as encryption keys, spreading codes) from the hardware, and transmit this information to a malicious party. To evade detection, such unauthorized communication can be hidden within legitimate bursts of transmit signal. In this paper, we present several signal processing techniques to detect unauthorized transmissions which can be hidden within the legitimate signal. We employ a scheme where the legitimate transmission is configured to emit a single sinusoidal waveform. We use time and spectral domain analysis techniques to explore the transmit spectrum. Since every transmission, no matter how low the signal power is, must have a spectral signature, we identify unauthorized transmission by eliminating the desired signal from the spectrum after capture. Experiment results how that when spread spectrum techniques are used, the presence of an unauthorized signal can be determined without the need for decoding the malicious signal. The proposed detection techniques need to be used as enhancements to the regular testing and verification procedures if hardware security is a concern.

Learning From Sleeping Experts: Rewarding Informative, Available, and Accurate Experts

We consider a generalized model of learning from expert advice in which experts could abstain from participating at some rounds. Our proposed online algorithm falls into the class of weighted average predictors and uses a time varying multiplicative weight update rule. This update rule changes the weight of an expert based on his relative performance compared to the average performance of available experts at the current round. This makes the algorithm suitable for recommendation systems in the presence of an adversary with many potential applications in the new emerging area of Internet of Things. We prove the convergence of our algorithm to the best expert, defined in terms of both availability and accuracy, in the stochastic setting. In particular, we show the applicability of our definition of best expert through convergence analysis of another well-known algorithm in this setting. Finally, through simulation results on synthetic and real datasets we justify the out-performance of our proposed algorithms compared to the existing ones in the literature.

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